chip select weirdness

[thomastaranowski]

I've got a device I've mapped using cs[1].
//Code excerpt
//The netburner puts 16-bit values out on address lines
[16:32], bit 0 corresponds to address line 16.

static volatile unsigned short* inlatch = (volatile unsigned
short*)0xc0000018;

sim.cs[1].csar = REMOTE_MANAGER_BASE_ADDR>>16;
sim.cs[1].cscr = 0x0180;
sim.cs[1].csmr = 0x001f0001;

I can read *inlatch just fine, but only in normal user code. When I
try to read from it from an ISR, I always get 0. I've tried
re-reading it, disabling cache, all manner of volatile variables, and
my special variable-reading dance. Now, I see that the csmr register
has some settings that regulate access control, and the CPU
space/interrupt acknowledge cycle mask looks really guilty. However,
I'm certain it's set correctly, and I've compared it against other
csmr settings (from google, and ioboard.c), and it's consistent. I
also scanned the errata, and didn't see anything relevant.

Does anyone have some ideas on what I'm doing wrong?

relevant interrupt setup snippets
INTERRUPT(ple_handler,0x2600) { ... }
SetIntc( 0, ( long ) & ple_handler, 1, 1, 1 );

[rnixon]

It seems like you covered all the volatile stuff. How about using a scope and looking at the value of D16 (i'm assuming you mean data bus, not address bus) on one channel, and /cs1 on the other, just to verify the signal is what you think it is? If you have a scope with more than 2 channels, I would add the irq line as well.

[thomastaranowski]

Some additional information related to this problem...

I put the scope on the CS1 (and the corresponding address lines), and didn't see it toggle when reading from it in the ISR like it does when reading from my slow poll task running in normal user mode. It feels like I'm setting up the access mask in the chip select register incorrectly, but I've verified it manually, and with some cfinit tool I found online and via newsgroups so many times I'm starting to dream about the cscr register I'm wondering if there's some other register that controls access to memory while in the ISR that I'm not aware of. Has anyone tried toggling the LEDs on a dev board in an ISR? That uses a chip select as well, and am wondering if it's some limitation I just don't know about. although that seems unlikely.

I should also mention that the device I have mapped in is a latch register I read in (inlatch) from the ISR. I also have an outlatch register I write to, and there is no problem with that.