System clock coupling onto ethernet cable

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greengene
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Location: Lakeside, CA

System clock coupling onto ethernet cable

Post by greengene »

just failed an emi test because of the cpu clock frequency being emitted
over the ethernet cable from mod5270. checked the mod5282 and it wasn't
as bad - well our product using that model did pass emi testing previously.

any ideas to help with this problem? shielded ethernet cable should help
but would really like to get to the root cause. we did in-house testing looking
at the dev boards and they were noisy too though not as high. also a 3x
harmonic is pretty big coming out too.

i'm just a s/w guy, but anything with the NB is my problem...
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yevgenit
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Re: System clock coupling onto ethernet cable

Post by yevgenit »

1. Verify, that the metal case of mod5270 Ethernet connector is connected to the metal case of the entire device.

2. Minimize the space between the metal case of mod5270 Ethernet connector and the metal case of the entire device.
In case of the space is more than a half millimeter, close the space with metalized glued strip.

3. It's assumed, that the metal case of the entire device is grounded and hasn't other holes near the mod5270 module.

Above solutions were helped to pass the EMI test in one of my projects.
Yevgeni Tunik
Embedded/RealTime software engineer
https://www.linkedin.com/in/yevgenitunik/
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greengene
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Location: Lakeside, CA

Re: System clock coupling onto ethernet cable

Post by greengene »

well, i think we violate all of those, as we did on our 5282 version.
expediency is pointing to just adding a notch filter.
we can do it the right way the next time...
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lgitlitz
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Re: System clock coupling onto ethernet cable

Post by lgitlitz »

I might have a quick software fix for you. It is definitely not guaranteed to fix your problem but worth trying before you do any major hardware revisions. This code will enable the spread spectrum feature of the of the clock and will reduce EMI coming from the CPU PLL. You may want to look at the clock chapter of the reference manual and experiment with different values for the defines at the top of this code. I also lower all the available GPIO drive strengths registers, this can sometimes help with EMI.

Code: Select all

/**************************************************************/
// The Following section of code turns on the spread spectrum
//   for the PLL and also reduces pin drive strengh
// This should be used to reduce EMI emissions   
/**************************************************************/
   #define FM_RATE (0x1000)   // fref/40
   //#define FM_RATE (0)         // fref/80
   
   //#define FM_DEPTH   (0)         // FM disabled
   //#define FM_DEPTH   (0x400)      // 1% of fsys\2
   #define FM_DEPTH   (0x800)      // 2% of fsys\2
   
   #define FM_EXP (128)
      
   #define SYNSR_LOCK_BIT 0x00000008
   
   //sim.clock.syncr |= 0x8000;
   sim.gpio.dscr_eim = 0;
   sim.gpio.dscr_feci2c = 0;
   sim.gpio.dscr_uart = 0;
   sim.gpio.dscr_qspi = 0;
   sim.gpio.dscr_timer = 0;

   //syncr factory setting = 0x03000000, MFD = 011, RFD = 000
   sim.clock.syncr |= FM_EXP; // set to calculated EXP
   sim.clock.syncr &= ~0x00000C00; // Clear Depth fields to disable modulation
   while((sim.clock.synsr & SYNSR_LOCK_BIT) != SYNSR_LOCK_BIT);  //wait to lock
   
   sim.clock.syncr |= 0x00080000; //MFD = 011, RFD = 001
   sim.clock.syncr |= ( FM_RATE | FM_DEPTH); 
   while((sim.clock.synsr & SYNSR_LOCK_BIT) != SYNSR_LOCK_BIT);  //wait to lock
   
   sim.clock.syncr &= ~0x00080000; //MFD = 011, RFD = 000
   
   while((sim.clock.synsr & 2) != 2);  // Wait for calibration to be done

/********************************************************************/
// EMI reduction code done
/**************************************************************/
   
   OSTimeDly(2);
   
   if((sim.clock.synsr & 1) == 1)
      printf("Frequency Modulation of Clock Successfully Calibrated!\r\n");
   else
      printf("Frequency Modulation of Clock FAILED Calibration!\r\n");
   
greengene
Posts: 164
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Location: Lakeside, CA

Re: System clock coupling onto ethernet cable

Post by greengene »

AWESOME!
thanks, larry!
that knocked 17 db off the spike at the clock frequency!

it looks like another pass through the freescale manuals is required.
i'm sure that section was skipped over with, i'll never need this stuff...

thanks again - woohoo!!!!
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lgitlitz
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Re: System clock coupling onto ethernet cable

Post by lgitlitz »

You are welcome. I calculated what I thought the values should be from the manual. Then I tested it out with a spectrum analyzer and a PK70. The values I calculated where off pretty far from the values that worked best according to the spectrum analyzer. I think the values set right now are the ones that tested the best while experimenting. The section in the reference manual is only a page or two. Hopefully this gets you under the EMI noise level you require.
khoney
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Re: System clock coupling onto ethernet cable

Post by khoney »

We had EMI issues with a Netburner module as well (the 5270). It was interfering with a sensitive receiver circuit. We were not using the CLKOUT or any of the external address/data lines, so we helped our situation somewhat by removing all of the pins on left side of the board with the exception of GND, 3,3V, RSTO and RSTI. I sure wish Netburners could be purchased without the header soldered on. It would also be cool if there was a 'low emi' version that didn't bring the external bus (and possibly CLKOUT) onto the header. Those pins make great little antennas!
rnixon
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Joined: Thu Apr 24, 2008 3:59 pm

Re: System clock coupling onto ethernet cable

Post by rnixon »

If you don't need the left header, what other pins on the right header do you need? Would a SB70LC work? it has just 20 pins: serial i/o, gpio, spi, i2c, and others I don't recall.
seulater
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Re: System clock coupling onto ethernet cable

Post by seulater »

just curious, would it not be easier to put a shielded cage either around your receiver or NB module than to remove the header ?
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