Problems using EPORT IRQ5 and IRQ7 on MOD5270

[lgitlitz]

I just ran a quick test on a MCF5234 and nested interrupts seem to work with the EPORT pins set as inputs. My test will enter a level 1 interrupt on the negative edge of IRQ1. The mask is set to 2100 so only level 1 interrupts are blocked. The interrupt will wait for IRQ1 to go high before leaving the interrupt. IRQ5 will set IRQ5_Fired true in its interrupt routine only if the IRQ1 interrupt is active. It shows that nesting is working.

You mentioned that in your test you always lose IRQ1 while IRQ3 is actively servicing its interrupt. This will always be true since the interrupt mask must be set to at least 0x2300 for a level 3 interrupt and only a level 4 or higher can nest into it. You should be able to nest your IRQ3 interrupt into your IRQ1 interrupt as long as you set the interrupt mask to 0x2100 or 0x2200 for IRQ1. For example, in my code when I set the mask level of the IRQ1 interrupt to 0x2500 then I can not nest my IRQ5 since it is now blocked while the IRQ1 is active.

Code: Select all

volatile BOOL IRQ1_Active = FALSE;
volatile BOOL IRQ1_Fired = FALSE;
volatile BOOL IRQ5_Fired = FALSE;

INTERRUPT( IRQ1_isr, 0x2100 )
{
   IRQ1_Active = TRUE;
   while(( sim.eport.eppdr & 0x2 ) == 0 ); // Stay here till IRQ line is high so I can trigger IRQ5
   IRQ1_Fired = TRUE;
   IRQ1_Active = FALSE;
   sim.eport.epfr = 0x02; // 0000 0010 - Clear the interrupt edge
}
INTERRUPT( IRQ5_isr, 0x2500 )
{
   if( IRQ1_Active )
      IRQ5_Fired = TRUE;
   sim.eport.epfr = 0x20; // 0010 0000 - Clear the interrupt edge
}

usermain.... ->
    J2[43].function( PINJ2_43_IRQ1_FET );
    J2[47].function( PINJ2_47_IRQ5_FET );
    SetIntc( 0, ( long ) &IRQ1_isr, 1, 1, 1 );
    SetIntc( 0, ( long ) &IRQ5_isr, 5, 5, 5 );
    sim.eport.epier = 0x22; // 0000 0010 - Enable IRQ1 IRQ5

    while (1) {
       if( IRQ1_Fired )
       {
          iprintf("TimeTick = %d\r\n", TimeTick);
          iprintf("IRQ1 has fired\r\n");
          if( IRQ5_Fired )
             iprintf("The nested IRQ5 has also fired\r\n");
          IRQ1_Fired = FALSE;
          IRQ5_Fired = FALSE;
       }
        OSTimeDly(10);
    }

[bbracken]

When the IRQ3 interrupt occurs, the code saves the current interrupt mask and sets the interrupt mask to 4, resets the IRQ3 interrupt, executes the user ISR, restores the interrupt mask and exits the interrupt. If IRQ1 occurs during this process, the interrupt should be held off until the IRQ3 interrupt completes. The pending IRQ1 (Level 1 interrupt) should now get serviced.

bb

[lgitlitz]

I think I see what you are saying now. The IRQ1 should occur as soon as the IRQ3 routine returns but this is not happening. Instead the processor is not recognizing the IRQ1 that occurred during the IRQ3 interrupt and it is completely lost. I just modified the test I made. I now hold in the IRQ5 interrupt until the signal goes high. If I now trigger IRQ1 I see that the interrupt does occur as soon as the IRQ5 routine returns, I do not lose this interrupt. I will try to test this on one of our MCF52236 processors tomorrow to see if I can get results like you are seeing. Are you sure you are not clearing more bit in the EPORT flag register when you leave the interrupt?

[bbracken]

The correct EPORT register is being used to reset the correct interrupt. It appears that although there are 4 seperate EPORT channels (I'm using an MCF52259), the EPORT IP is only capabable of handling 1 interrupt source at a time. My IRQ1 and IRQ3 project works fine... .as long as the IRQs do not overlap.

bb