Dear All,
I just came into contact with MOD5270, and then I came across the information left by the previous employees who resigned. I have checked the MCF5271 Datasheet, but I still don’t understand why the following three memory indicators can be mapped to /CS1 /CS2 /CS3. Please help me if you are familiar with MOD5270. I also bought the MOD5270 LC Development Kit. I hope to have a better understanding of the operating mechanism of MOD5270 after using this development board.
// #define BASE_ADDR 0xA0000000
#define SRAM_BASE_ADDR 0xB0000000 // A100_0000 ~ A7FF_FFFF, 16 MBytes
#define FPGA_BASE_ADDR 0xB2000000 // A800_0000 ~ A8FF_FFFF, 1 Mbytes
#define FIFO_BASE_ADDR 0xB4000000 // A800_0000 ~ A8FF_FFFF, 1 Mbytes
Sincerely,
SY.Chen
MOD5270 /CS1 /CS2 /CS3 Memory Address Mapping Issue
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- Posts: 4
- Joined: Wed Sep 06, 2023 1:49 am
Re: MOD5270 /CS1 /CS2 /CS3 Memory Address Mapping Issue
Other than for initial BOOT the memory map of the 5270 is almost completely programmable.
The default values for the Netburner environment...
dram (rwx) : ORIGIN = 0x02000000, LENGTH = 0x200000
SRAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0xFFFF //Holds Vector table and some boot info... as well
sim = 0x40000000; //IE device hardware registers
flash 0xffc00000 //Boot, userparam and other stuff in here, but starts at this address..
0xB0000000 does not map into any of these regions, so +
So the other person just picked an area that was unoccupied and assigned the addresses there...
The default values for the Netburner environment...
dram (rwx) : ORIGIN = 0x02000000, LENGTH = 0x200000
SRAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0xFFFF //Holds Vector table and some boot info... as well
sim = 0x40000000; //IE device hardware registers
flash 0xffc00000 //Boot, userparam and other stuff in here, but starts at this address..
0xB0000000 does not map into any of these regions, so +
So the other person just picked an area that was unoccupied and assigned the addresses there...
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- Posts: 4
- Joined: Wed Sep 06, 2023 1:49 am
Re: MOD5270 /CS1 /CS2 /CS3 Memory Address Mapping Issue
Thank you for your reply, but you still don't know how I should make /CS1 or /CS2 or /CS3 produce Falling Pulse. I currently want to use NetBurner MOD5270 Address Bus & Data Bus & /CS2 to communicate with the Spartan3E FPGA Board designed by my company. What I want to know most is how I should write to which Address Bus & Data Bus, and then let /CS2 generate Falling Pulse. If possible, I would prefer to have a sequence timing diagram. I really need your help. Thank you again for your trouble.
In addition, can you tell me how to control the operating frequency of MOD5270 MCU? Are there any registers that can specifically set the operating frequency of MOD5270? Thank you again ~
Sicerely,
SY.Chen (you can call me "Abraham")
In addition, can you tell me how to control the operating frequency of MOD5270 MCU? Are there any registers that can specifically set the operating frequency of MOD5270? Thank you again ~
Sicerely,
SY.Chen (you can call me "Abraham")
Re: MOD5270 /CS1 /CS2 /CS3 Memory Address Mapping Issue
If you mess with the operating frequency many things in the system will break.
(Serial ports, time etc..)
Why do you want to change the frequency?
Have the chipselects already been setup?
sim.cs[1].csar=.....
etc...
If not read the MCF5270 reference manual:
nburn\docs\FreescaleManuals\MCF5270_5271RM.pdf
Specifically chapter 16.
The 3 chipselect reggisters are accessable....
#include <sim5270.h>
sim.cs[1].csar=
sim.cs[1].csmr=
sim.cs[1].cscr=
Where CS1 = cs[1]... cs[2].... etc...
Assuming that the CS has been setup (given your predesesor has assigned addresses they probably have been)
I'll assume these are setup as 16 bit WORD wide registers... replace WORD with BYTE is they are 8 bits.
volatile WORD * pCSFPGA=(WORD *) FPGA_BASE_ADDR;
pCSFpga[0]=0x12324; /Wrtites 234 to address zero of CS assigned to FPGA_BASE_ADDR
WORD w;
w=pCSFpga[0]; //Read from address 0
w=pCSFpga[n] //Read from address N
Can you post how the CS registers are setup and I'll tell you the exact structures and how the address bits are going to corespond..
(Serial ports, time etc..)
Why do you want to change the frequency?
Have the chipselects already been setup?
sim.cs[1].csar=.....
etc...
If not read the MCF5270 reference manual:
nburn\docs\FreescaleManuals\MCF5270_5271RM.pdf
Specifically chapter 16.
The 3 chipselect reggisters are accessable....
#include <sim5270.h>
sim.cs[1].csar=
sim.cs[1].csmr=
sim.cs[1].cscr=
Where CS1 = cs[1]... cs[2].... etc...
Assuming that the CS has been setup (given your predesesor has assigned addresses they probably have been)
I'll assume these are setup as 16 bit WORD wide registers... replace WORD with BYTE is they are 8 bits.
volatile WORD * pCSFPGA=(WORD *) FPGA_BASE_ADDR;
pCSFpga[0]=0x12324; /Wrtites 234 to address zero of CS assigned to FPGA_BASE_ADDR
WORD w;
w=pCSFpga[0]; //Read from address 0
w=pCSFpga[n] //Read from address N
Can you post how the CS registers are setup and I'll tell you the exact structures and how the address bits are going to corespond..
Re: MOD5270 /CS1 /CS2 /CS3 Memory Address Mapping Issue
Hello,
Some background information would help us provide a better answer. You mention an existing project. Is that project currently working and you want to make changes, or is this for a new project?
If the existing project needs to be changed, can you provide details on what you want to do?
The address map is located here:
\nburn\docs\Platform\Mod5270.pdf
There is a h/w app note on the data bus here:
https://www.netburner.com/download/mod5 ... ign-notes/
Some background information would help us provide a better answer. You mention an existing project. Is that project currently working and you want to make changes, or is this for a new project?
If the existing project needs to be changed, can you provide details on what you want to do?
The address map is located here:
\nburn\docs\Platform\Mod5270.pdf
There is a h/w app note on the data bus here:
https://www.netburner.com/download/mod5 ... ign-notes/