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parameter base_addr = 32'h10000000;  //base address of external memory
reg [31:0]FB_Address;               // register to store latched address
reg [31:0]MyWriteReg ;             // Stores data when MOD5441x writes to address 0x10000010

//  If the flexbus chip select is inactive or flexbus output enable is inactive 
//  then we drive nothing on flexbus data line 
//  otherwise we use function func_FB_Dataout to decide what we drive on flexbus data lines 
//  Refer to MCF54415 Flexbus chapter for basic bus cycle diagrams

assign { FB_Bus[31:0] } =  ( (FB_N_CS1==1) || (FB_N_OE==1) ) ?  32'bz : func_FB_Dataout( FB_Address );

function [31:0] func_FB_Dataout( input [31:0] address );
    case ( address[31:0] )
        base_addr + 32'h100 :   func_FB_Dataout = 32'h01234567;  // If reading address 0x10000100 output 0x01234567
        base_addr + 32'h104 :   func_FB_Dataout = 32'h89ABCDEF;  // If reading address 0x10000104 output 0x89ABCDEF
        default :               func_FB_Dataout = address;                   // Any other address output the address
    endcase        
endfunction

// On every clock cycle that the chip select is not enabled, latch the address
// Since the CS is not asserted until after the address cycle, we will always have a latched address at CS assertion
// Once the chip select is active, check if the FPGA is being written to by the MOD5441x at a valid write address and save the data
always @(posedge FB_CLK)
begin
    if( FB_N_CS1 == 1 )
    begin
        FB_Address[31:0] <= FB_Bus[31:0];
    end
    else if ( FB_RNW == 0 )
    begin
        case( FB_Address )
            base_addr + 32'h010 :   MyWriteReg <= FB_Bus;  // example of a write operation from the MOD to the FPGA at address 0x10000010
            default : ;
        endcase
    end
end