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Mod5270 Powerup Crash

Posted: Tue Aug 07, 2012 3:40 pm
by sblair
I'm seeing an issue happen pretty repeatedly here on some boards. We are using a Mod5270 Core with our own carrier board.

I've got one set that pretty frequently exhibits this issue and another unit that doesn't exhibit it at all. Same hardware and power supply model on both.

When I power up the unit it doesn't boot. Looking at the serial port I'm getting this:
Trap occured
Vector=Illegal Instruction FMT =00 SR =2700 FS =00
Faulted PC = FFC01360
D0:0200B220 02003220 4BFFEFD7 00000000 00007C24 D31BEB9F CF206080 15001080
A0:20000400 FFFBF4C6 BD65BF1F 5583FDBF 7F81F7F7 77DEEFFF F6DADFFB 2000FFF0
Waiting 2sec to start 'A' to abort
Error checksum fail
No Valid app


Netburner MOD5270B Monitor V1.03 Feb 28 2011 08:51:04
HELP for help
nb>
If I hit the CPU reset then it will boot correctly everytime after that. I can try doing a power cycle again and sometimes it will come up and sometimes it just does this again. Any thoughts? Clearly there is a valid app in the Flash. I'm guessing a weird power transient on powerup is occurring. Any suggestions on how to cope with it?

Thanks.
Scott

Re: Mod5270 Powerup Crash

Posted: Tue Aug 07, 2012 4:33 pm
by rnixon
What signals does your board use? Address or Data bus? If so, what's connected t them?

Re: Mod5270 Powerup Crash

Posted: Tue Aug 07, 2012 4:49 pm
by sblair
So I think the issue may be related to an FPGA we have on the carrier board. I've got one board without the FPGA stuffed that is working a 100% and the board with the issue has an FPGA on it.

The FPGA connects to the Address and Data bus.

Re: Mod5270 Powerup Crash

Posted: Wed Aug 08, 2012 11:02 am
by pbreed
The 5270 needs to read the Flash over the address and data bus, and the SDRAM is on the Address and data bus.
So if your FPGA is doing anything on the address and data bus prior to being addressed by the CPU
then that is your problem. The cleanest solution is to add a bidirectional bus buffer between the D16..D31 and the the FPGA.
That bus buffer should be enabled by the TIP signal.

Since the FPGA takes a awhile to initialize tieing the FPGA done initalizing signal to the RSTI in signal is the most common solution to that part of the dilemma....


Paul