A little explanation for the uninitiated: the MCF54415 processor on these modules runs at a default core clock speed of 250 MHz. This is generated using a PLL in the processor from a 25 MHz crystal on the module. This 250 MHz core clock is then scaled by a factor of 2 to 125 MHz to create the clock signal that is fed into the peripheral modules of the processor. These modules are then clocking and drawing power at some subharmonic of 125 MHz. By disabling the clock to a peripheral module, that module will no longer have a varying load; it may still draw some power, but significantly less, and more importantly, it will do so in a DC manner.
So how do you do this? By writing to the Peripheral Power Management Registers (MCF54415 Reference Manual 9.2) and turning on the bit associated with the peripheral module. You can do an 'all at once', by read, modify, writing to the Peripheral Power Management Registers (section 9.2.4) or you can selectively enable/disable modules one at a time by writing to the Peripheral Power Management Clear (section 9.2.3) or the Peripheral Power Management Set (section 9.2.2).
I have made a header file which will facilitate this process. It defines macros that will write to the Set/Clear register pair to individually disable/enable modules. The format of the macros are as follows:
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PERIPH_DISABLE_<MODULE NAME>
PERIPH_ENABLE_<MODULE NAME>
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PERIPH_DISABLE_FLEXBUS
PERIPH_ENABLE_FLEXBUS
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PERIPH_DISABLE_<MODULE NAME>_<SUBMODULE NUMBER>
PERIPH_ENABLE_<MODULE NAME>_<SUBMODULE NUMBER>
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PERIPH_DISABLE_DSPI_1
PERIPH_ENABLE_DSPI_1