Reducing clock speed of Nano54415

[khoney]

When I was working with the MOD5270, I needed to investigate running the module at lower clock speeds. Larry made an excellent example that I was able to directly use to try running at various clock speeds. I've now ported to the Nano module running at the default system clock. Have any clock reduction examples been written for the 54415 series? I'm trying to cut the system clock speed in half (by making sysclk=125MHz and busclk=62.5Mhz), but so far have not had success.

[pbreed]

The DDR memory used on the nano has a minimum clock rate....
I'm not sure that reducing clock rate on the Nano is going to work....


Paul

[khoney]

If you have a part number, I'd appreciate it (don't want to peel off the MAC sticky). I'm mainly looking at ways to reduce current and/or emissions.

One of the things I've seen is that the drive strength to the SDRAM can be reduced to 1/2 current by setting (sim1.gpio.mscr_sdramc = 0x00). According to the 54415 data sheet this is the suggested setting if interfacing to a single device, i.e. not using a DIMM.

I'm also looking at turning off all unused peripherals. It appears that somewhere in the startup code many of these peripherals are enabled (talking about the ppmlr0, ppmhr0, ppmlr1, and ppmhr1 registers in the scm structure). Is there by any chance any documentation on which peripherals are required in order to operate the Nano module (aside from application-specific peripherals)? That is to say, which peripherals are required for bootup and OS operation?

I've been able to turn off the clocks for the eSDHC, NAND, and USB controllers by setting sim2.clock.pll_dr=0x00000061 with no apparent ill effect. I've also been able to disable individual peripherals by modifying the aforementioned PPMxRx registers. However, sometimes when I do this, it causes a watchdog timeout.

The code I'm running is as follows:

Code: Select all

sim1.gpio.mscr_sdramc = 0x00;   // Set drive strength of SDRAM interface to 1/2 current.
sim2.clock.pll_dr = 0x00000061;  // Turn off eSDHC, NAND and USB controller clocks

USER_ENTER_CRITICAL();
sim2.scm.ppmlr0 |= 0xE802C304;  // Disable DMA Timers 1-3, UART3, eDMA Ctrl, DSPI1, I2C1, FlexCAN, and FlexBus 
sim2.scm.ppmlr1 |= 0x3F00C0F4;  // Disable 1-wire, I2C 2-5, DSPI2, DSPI3, UART4-9

sim2.scm.ppmhr0 |= 0xFF9E3FFE; // Disable NAND, eth sw, eSDHC, SSI1, RNG, USB OTG, USB Host,
                                              // SIM, RTC, DAC0, ADC, Edge port, PIT1, PIT2, PIT3
 
sim2.scm.ppmhr1 |= 0xFFFFFFCF; // Disable mcPWM
USER_EXIT_CRITICAL();

[pbreed]

Only the DSPI and Pit 0 timer and DDR ram should be necessary...
The DSPI is not needed once boot is done unless one runs autoupdate, ipsetup or saveuserparams...

You can turn that back on by capturing the FlashProgram, FlashErase in the FlashOps.cpp file.

I believe that the drive strength is by default low....

The DDR chip is either: (I believe the first batches were all ISSI with 90% confidence)

ISSI: IS43DR86400B-3DBLI
Micron : MT47H64M8CF-25E IT


Paul

[khoney]

Thanks, Paul.

According to the datasheet, the reset value for SDRAM drive strength is supposed to be 0x03 (2 lsbs indicate RESERVED status). However, after the system comes up, I read back a value of 0x01, which is full strength. Either the datasheet is incorrect or it must be getting altered somewhere?