Porting to Nano54415: Issues and questions

[khoney]

With the Nano's include file, my I2Cxxx function calls are being redefined as Master_I2Cxxx function calls, but I get undefined reference errors when I build my project. I've tried rebuilding system files, but the problem remains. Is there some other step I need to take? I'm trying to port from a 5270 to a Nano ASAP.

P.S. - While trying to port my code, I've discovered that the Nano's sim file does not define some of the EPORT registers that are in the Freescale manual (such as the Data Direction Register).

[seulater]

P.S. - While trying to port my code, I've discovered that the Nano's sim file does not define some of the EPORT registers that are in the Freescale manual (such as the Data Direction Register).

The nano is a very different animal. Look in the sim5441x.h file for the registers. here is a small snippet of it.

Code: Select all

typedef struct {
   vubyte  podr_a;          /* 0xEC09_4000 -> 0xEC09_4000 - Port Output Data Register A                             */
   vubyte  podr_b;          /* 0xEC09_4001 -> 0xEC09_4001 - Port Output Data Register B                             */
   vubyte  podr_c;          /* 0xEC09_4002 -> 0xEC09_4002 - Port Output Data Register C                             */
   vubyte  podr_d;          /* 0xEC09_4003 -> 0xEC09_4003 - Port Output Data Register D                             */
   vubyte  podr_e;          /* 0xEC09_4004 -> 0xEC09_4004 - Port Output Data Register E                             */
   vubyte  podr_f;          /* 0xEC09_4005 -> 0xEC09_4005 - Port Output Data Register F                             */
   vubyte  podr_g;          /* 0xEC09_4006 -> 0xEC09_4006 - Port Output Data Register G                             */
   vubyte  podr_h;          /* 0xEC09_4007 -> 0xEC09_4007 - Port Output Data Register H                             */
   vubyte  podr_i;          /* 0xEC09_4008 -> 0xEC09_4008 - Port Output Data Register I                             */
   vubyte  podr_j;          /* 0xEC09_4009 -> 0xEC09_4009 - Port Output Data Register J                             */
   vubyte  podr_k;          /* 0xEC09_400A -> 0xEC09_400A - Port Output Data Register K                             */
   vubyte  pack00;          /* 0xEC09_400B -> 0xEC09_400B - RESERVED                                                */
   vubyte  pddr_a;          /* 0xEC09_400C -> 0xEC09_400C - Port Data Direction Register A                          */
   vubyte  pddr_b;          /* 0xEC09_400D -> 0xEC09_400D - Port Data Direction Register B                          */
   vubyte  pddr_c;          /* 0xEC09_400E -> 0xEC09_400E - Port Data Direction Register C                          */
   vubyte  pddr_d;          /* 0xEC09_400F -> 0xEC09_400F - Port Data Direction Register D                          */
   vubyte  pddr_e;          /* 0xEC09_4010 -> 0xEC09_4010 - Port Data Direction Register E                          */
   vubyte  pddr_f;          /* 0xEC09_4011 -> 0xEC09_4011 - Port Data Direction Register F                          */
   vubyte  pddr_g;          /* 0xEC09_4012 -> 0xEC09_4012 - Port Data Direction Register G                          */
   vubyte  pddr_h;          /* 0xEC09_4013 -> 0xEC09_4013 - Port Data Direction Register H                          */
   vubyte  pddr_i;          /* 0xEC09_4014 -> 0xEC09_4014 - Port Data Direction Register I                          */
   vubyte  pddr_j;          /* 0xEC09_4015 -> 0xEC09_4015 - Port Data Direction Register J                          */
   vubyte  pddr_k;          /* 0xEC09_4016 -> 0xEC09_4016 - Port Data Direction Register K                          */
   vubyte  pack01;          /* 0xEC09_4017 -> 0xEC09_4017 - RESERVED                                                */
   vubyte  ppdsdr_a;        /* 0xEC09_4018 -> 0xEC09_4018 - Port Pin Data/Set Data Register A                       */
   vubyte  ppdsdr_b;        /* 0xEC09_4019 -> 0xEC09_4019 - Port Pin Data/Set Data Register B                       */
   vubyte  ppdsdr_c;        /* 0xEC09_401A -> 0xEC09_401A - Port Pin Data/Set Data Register C                       */
   vubyte  ppdsdr_d;        /* 0xEC09_401B -> 0xEC09_401B - Port Pin Data/Set Data Register D                       */
   vubyte  ppdsdr_e;        /* 0xEC09_401C -> 0xEC09_401C - Port Pin Data/Set Data Register E                       */
   vubyte  ppdsdr_f;        /* 0xEC09_401D -> 0xEC09_401D - Port Pin Data/Set Data Register F                       */
   vubyte  ppdsdr_g;        /* 0xEC09_401E -> 0xEC09_401E - Port Pin Data/Set Data Register G                       */
   vubyte  ppdsdr_h;        /* 0xEC09_401F -> 0xEC09_401F - Port Pin Data/Set Data Register H                       */
   vubyte  ppdsdr_i;        /* 0xEC09_4020 -> 0xEC09_4020 - Port Pin Data/Set Data Register I                       */
   vubyte  ppdsdr_j;        /* 0xEC09_4021 -> 0xEC09_4021 - Port Pin Data/Set Data Register J                       */
   vubyte  ppdsdr_k;        /* 0xEC09_4022 -> 0xEC09_4022 - Port Pin Data/Set Data Register K                       */
   vubyte  pack02;          /* 0xEC09_4023 -> 0xEC09_4023 - RESERVED                                                */
   vubyte  pclrr_a;         /* 0xEC09_4024 -> 0xEC09_4024 - Port Clear Output Data Register A                       */
   vubyte  pclrr_b;         /* 0xEC09_4025 -> 0xEC09_4025 - Port Clear Output Data Register B                       */
   vubyte  pclrr_c;         /* 0xEC09_4026 -> 0xEC09_4026 - Port Clear Output Data Register C                       */
   vubyte  pclrr_d;         /* 0xEC09_4027 -> 0xEC09_4027 - Port Clear Output Data Register D                       */
   vubyte  pclrr_e;         /* 0xEC09_4028 -> 0xEC09_4028 - Port Clear Output Data Register E                       */
   vubyte  pclrr_f;         /* 0xEC09_4029 -> 0xEC09_4029 - Port Clear Output Data Register F                       */
   vubyte  pclrr_g;         /* 0xEC09_402A -> 0xEC09_402A - Port Clear Output Data Register G                       */
   vubyte  pclrr_h;         /* 0xEC09_402B -> 0xEC09_402B - Port Clear Output Data Register H                       */
   vubyte  pclrr_i;         /* 0xEC09_402C -> 0xEC09_402C - Port Clear Output Data Register I                       */
   vubyte  pclrr_j;         /* 0xEC09_402D -> 0xEC09_402D - Port Clear Output Data Register J                       */
   vubyte  pclrr_k;         /* 0xEC09_402E -> 0xEC09_402E - Port Clear Output Data Register K                       */
   vubyte  pack03;          /* 0xEC09_402F -> 0xEC09_402F - RESERVED                                                */
   vuword  pcr_a;           /* 0xEC09_4030 -> 0xEC09_4031 - Pull Control Register A                                 */
   vuword  pcr_b;           /* 0xEC09_4032 -> 0xEC09_4033 - Pull Control Register B                                 */
   vuword  pcr_c;           /* 0xEC09_4034 -> 0xEC09_4035 - Pull Control Register C                                 */
   vuword  pcr_d;           /* 0xEC09_4036 -> 0xEC09_4037 - Pull Control Register D                                 */
   vuword  pcr_e;           /* 0xEC09_4038 -> 0xEC09_4039 - Pull Control Register E                                 */
   vuword  pcr_f;           /* 0xEC09_403A -> 0xEC09_403B - Pull Control Register F                                 */
   vuword  pcr_g;           /* 0xEC09_403C -> 0xEC09_403D - Pull Control Register G                                 */
   vuword  pcr_h;           /* 0xEC09_403E -> 0xEC09_403F - Pull Control Register H                                 */
   vuword  pcr_i;           /* 0xEC09_4040 -> 0xEC09_4041 - Pull Control Register I                                 */
   vuword  pcr_j;           /* 0xEC09_4042 -> 0xEC09_4043 - Pull Control Register J                                 */
   vuword  pcr_k;           /* 0xEC09_4044 -> 0xEC09_4045 - Pull Control Register K                                 */

[khoney]

I did look there, and I had to add three registers to the eportstruct typedef to match the 54415 register definition in MCF54415RM.pdf. The sim5441x.h file had them as reserved.

seulater - have you been able to use any I2C interface calls for the Nano? I still haven't figured out how to fix this problem.

[seulater]

ya, i got it working.

Copy "i2cmaster.cpp" into your project, and include #include <i2cmaster.h>
I dont know why i have to bring in the "i2cmaster.cpp" file to the project, i cannot get it to compile without doing that.



Then initialize it with

// Init the I2C Periferral.
// NOTE: the default is for I2C0 if you need it on another port,
// Your going to have to dig into the code and change it.
I2CInit(0x3f); //BYTE freqdiv

then the regular stuff for write and read.
// Write
i2cStatus = I2CStart( CLOCK_ADDRESS , I2C_START_WRITE );
i2cStatus += I2CSend( reg );
i2cStatus += I2CSend( data );
i2cStatus += I2CStop();

//Read
i2cStatus = I2CStart( CLOCK_ADDRESS , I2C_START_WRITE );
i2cStatus += I2CSend( reg );
i2cStatus += I2CStop();

i2cStatus += I2CRestart( CLOCK_ADDRESS, I2C_START_READ );
i2cStatus += I2CReadBuf(CLOCK_ADDRESS, read_buffer, 1,true); // true also adds the stop bit

[khoney]

If anyone has successfully enabled the Rapid GPIO module on the 54415, I would appreciate a code snippet. I think I have everything set up correctly, except for enabling access to the module. I still have not been able to decipher the datasheet. I have tried this:

USER_ENTER_CRITICAL();
asm(" move.l #0x8C000035, %d0 ");
asm(" movec %d0, #0x009 ");
USER_EXIT_CRITICAL();

Followed by the sim writes to the rgpio registers. I must be missing something.

[khoney]

I think I have it working now. Need to learn to read better. The sim_rgpio.clr register needs to have the bit(s) it wants cleared set to 0, not 1, so I needed to add a ~ operator to my data value.

Edit: I should also mention that the sys.ld file in the platform's lib folder did not contain a required address definition, and it must be added. You will need to add the following line:

sim_rgpio = 0c8C000000;

[BBAdmin]

We have added a rapid gpio example to go out in the next release. I have attached the main.cpp file of the example.

[khoney]

Very nice example (wish I had it yesterday). I'm curious as to why you didn't use the sim_rgpio structure defined for the platform, since you are using the sim1 register for other things. It would have avoided duplicating the defines (except for your masks). When I implemented the rapid GPIO, I had to add the address definition to sys.ld (see my above post), but then I could use sim_rgpio.enb, sim_rgpio.dir0, sim_rgpio.data, sim_rgpio.clr, sim_rgpio.set, and sim_rgpio.tog as defined in the rgpiostruct in the sim5441x.h file. Since you went through the trouble of creating the structure in the first place, why not use it in your example?

Also, shouldn't the enabling of the processor access to RGPIO be surrounded by the critical entry/exit as well? My app didn't work unless I did that.