Netburner user application board schematic/design review

[vstamps]

Is it possible to have a proposed application board schematic reviewed for tips and techniques?
Virgil

[rnixon]

It looks like you can reply with attachments, so if you want to post it I think people will take a look.

[vstamps]

This is an interim step schematic and development board for our detector platform project to read analog samples from two signal sources approximately every 35uS. The signal path is through an anti-aliasing filter to an A/D and into a 16-bit wide x 256 deep fifo. The core will process data out of the fifo into box-car averaging and (for now) display the results via two D/A converters for scope diagnostics. A 3rd D/A channel will be controlling a high voltage required by the sensor system. The design uses the MOD5234 module. There is also a serial port and a slow A/D for other sensor measurements.

Another PIC processor (not on this board) is doing the timing and control of the data acquisition process.

We are at a point early in the project where we are evaluating and starting with this basics. We will develop our processing algorithms.

I have some discrete logic that should probably be in a FPGA but I am not ready to make that step now.


Virgil

[yevgenit]

You don't need external FIFO chip to measure each 35us the two analog channels.
My project uses mod5270 (147.456MHz of core frequency) and QSPI-connected MAX1270 ADC (25 serial clocks per measurement cycle). The faster reached sampling with wraparound mode is ~70kSamples/s with 2MHz serial clock. Actually, the application uses 20kSamples/s.
To prevent overwrite the first (of eight) samples, the early "queue finished" interrupt is arranged. QSPI has the issue: it generates the interrupt too late - after "delay after transfer" interval - instead of before this interval. In the other words, QSPI interrupt is generated by first falling edge of the ADC QSPI_CS. Tying the additional QSPI_CSx to the external interrupt pin (and some settings of QSPI and ePort) enables to generate "queue finished" interrupt by the last rising edge of the ADC QSPI_CS.
For details, see the post "Too late QSPI interrupt and the workaround " at
http://forums.freescale.com/freescale/b ... ad.id=4040
The ISR copies eight samples to the temporary RAM buffer. Then, the ISR releases the semaphore for the measurement task.
In case of ADC, which uses only 16 QSPI serial clocs, the timing is even more relaxed.
Each case, you will need to rewrite the QSPI driver.