In I2C Master RX mode, after End of ADDR Cycle, after Dummy Read from I2DR, responding to IIF, not Last Byte to be Read, after slave has released clock stretch (SCL tristated), what is it that starts the clock going again so that the slave can transmit another byte? Is it the clearing of IIF, or Read from I2DR?
The reason I'm asking is that I'm wondering about the lifetime of valid data in I2DR. When does it start getting overwritten with new bits?
Discussion to talk about software related topics only.
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