NetBurner 3.1
wm8904_reg.h
1 #ifndef __WM8904_REG_H
2 #define __WM8904_REG_H
3 /*NB_REVISION*/
4 
5 /*NB_COPYRIGHT*/
6 
7 #define WM8904_I2C_ID 0x1A
8 
9 #define BIAS_CTL0_ISEL_HI (0x2 << 2)
10 #define BIAS_CTL0_ISEL_LO (0x0 << 2)
11 #define BIAS_CTL0_BIAS_ENA (1 << 0)
12 
13 #define VMID_CTL0_BUF_ENA (1 << 6)
14 #define VMID_CTL0_RES_DIS (0 << 1)
15 #define VMID_CTL0_RES_MID (1 << 1)
16 #define VMID_CTL0_RES_SLOW (2 << 1)
17 #define VMID_CTL0_RES_FAST (3 << 1)
18 #define VMID_CTL0_ENA (1 << 0)
19 
20 #define PWR_MGMNT0_INL_ENA (1 << 1)
21 #define PWR_MGMNT0_INR_ENA (1 << 0)
22 
23 #define PWR_MGMNT2_HPL_PGA_ENA (1 << 1)
24 #define PWR_MGMNT2_HPR_PGA_ENA (1 << 0)
25 
26 #define PWR_MGMNT6_DACL_ENA (1 << 3)
27 #define PWR_MGMNT6_DACR_ENA (1 << 2)
28 #define PWR_MGMNT6_ADCL_ENA (1 << 1)
29 #define PWR_MGMNT6_ADCR_ENA (1 << 0)
30 
31 #define CHARGE_PUMP0_CP_ENA (1 << 0)
32 
33 #define CLK_SYS_RATE_64 (0 << 10)
34 #define CLK_SYS_RATE_128 (1 << 10)
35 #define CLK_SYS_RATE_192 (2 << 10)
36 #define CLK_SYS_RATE_256 (3 << 10)
37 #define CLK_SYS_RATE_384 (4 << 10)
38 #define CLK_SYS_RATE_512 (5 << 10)
39 #define CLK_SYS_RATE_768 (6 << 10)
40 #define CLK_SYS_RATE_1024 (7 << 10)
41 #define CLK_SYS_RATE_1408 (8 << 10)
42 #define CLK_SYS_RATE_1536 (9 << 10)
43 #define CLK_SAMPLE_RATE_8K (0 << 10)
44 #define CLK_SAMPLE_RATE_12K (1 << 10)
45 #define CLK_SAMPLE_RATE_16K (2 << 10)
46 #define CLK_SAMPLE_RATE_24K (3 << 10)
47 #define CLK_SAMPLE_RATE_32K (4 << 10)
48 #define CLK_SAMPLE_RATE_48K (5 << 10)
49 
50 #define CLK_MCLK_INV (1 << 15)
51 #define CLK_SYSCLK_SRC_MCLK (0 << 14)
52 #define CLK_SYSCLK_SRC_FLL (1 << 14)
53 #define CLK_TOCLK_RATE_DIV2 (0 << 12)
54 #define CLK_TOCLK_RATE_DIV1 (1 << 12)
55 #define CLK_OPCLK_ENA (1 << 3)
56 #define CLK_CLK_SYS_ENA (1 << 2)
57 #define CLK_CLK_DSP_ENA (1 << 1)
58 #define CLK_TOCLK_ENA (1 << 0)
59 
60 #define AUDIO_INTF0_DACL_DATINV (1 << 12)
61 #define AUDIO_INTF0_DACR_DATINV (1 << 11)
62 #define AUDIO_INTF0_DAC_BOOST(x) ((x&3) << 9)
63 #define AUDIO_INTF0_LOOPBACK (1 << 8)
64 #define AUDIO_INTF0_ADC_SRCL (1 << 7)
65 #define AUDIO_INTF0_ADC_SRCR (1 << 6)
66 #define AUDIO_INTF0_DAC_SRCL (1 << 5)
67 #define AUDIO_INTF0_DAC_SRCR (1 << 4)
68 #define AUDIO_INTF0_ADC_COMP (1 << 3)
69 #define AUDIO_INTF0_ADC_COMPMODE (1 << 2)
70 #define AUDIO_INTF0_DAC_COMP (1 << 1)
71 #define AUDIO_INTF0_DAC_COMPMODE (1 << 0)
72 
73 #define AUDIO_INTF2_OPCLK_DIV_1 (0 << 8)
74 #define AUDIO_INTF2_OPCLK_DIV_2 (1 << 8)
75 #define AUDIO_INTF2_OPCLK_DIV_3 (2 << 8)
76 #define AUDIO_INTF2_OPCLK_DIV_4 (3 << 8)
77 #define AUDIO_INTF2_OPCLK_DIV_5_5 (4 << 8)
78 #define AUDIO_INTF2_OPCLK_DIV_6 (5 << 8)
79 #define AUDIO_INTF2_OPCLK_DIV_8 (6 << 8)
80 #define AUDIO_INTF2_OPCLK_DIV_12 (7 << 8)
81 #define AUDIO_INTF2_OPCLK_DIV_16 (8 << 8)
82 #define AUDIO_INTF2_BCLK_DIV_1 (0 << 0)
83 #define AUDIO_INTF2_BCLK_DIV_1_5 (1 << 0)
84 #define AUDIO_INTF2_BCLK_DIV_2 (2 << 0)
85 #define AUDIO_INTF2_BCLK_DIV_3 (3 << 0)
86 #define AUDIO_INTF2_BCLK_DIV_4 (4 << 0)
87 #define AUDIO_INTF2_BCLK_DIV_5 (5 << 0)
88 #define AUDIO_INTF2_BCLK_DIV_5_5 (6 << 0)
89 #define AUDIO_INTF2_BCLK_DIV_6 (7 << 0)
90 #define AUDIO_INTF2_BCLK_DIV_8 (8 << 0)
91 #define AUDIO_INTF2_BCLK_DIV_10 (9 << 0)
92 #define AUDIO_INTF2_BCLK_DIV_11 (10 << 0)
93 #define AUDIO_INTF2_BCLK_DIV_12 (11 << 0)
94 #define AUDIO_INTF2_BCLK_DIV_16 (12 << 0)
95 #define AUDIO_INTF2_BCLK_DIV_20 (13 << 0)
96 #define AUDIO_INTF2_BCLK_DIV_22 (14 << 0)
97 #define AUDIO_INTF2_BCLK_DIV_24 (15 << 0)
98 #define AUDIO_INTF2_BCLK_DIV_25 (16 << 0)
99 #define AUDIO_INTF2_BCLK_DIV_30 (17 << 0)
100 #define AUDIO_INTF2_BCLK_DIV_32 (18 << 0)
101 #define AUDIO_INTF2_BCLK_DIV_44 (19 << 0)
102 #define AUDIO_INTF2_BCLK_DIV_48 (20 << 0)
103 
104 #define AUDIO_INTF1_AIFDAC_TDM_NORM (0 << 13)
105 #define AUDIO_INTF1_AIFDAC_TDM_TDM (1 << 13)
106 #define AUDIO_INTF1_AIFDAC_TDM_CHAN0 (0 << 12)
107 #define AUDIO_INTF1_AIFDAC_TDM_CHAN1 (1 << 12)
108 #define AUDIO_INTF1_AIFADC_TDM_NORM (0 << 11)
109 #define AUDIO_INTF1_AIFADC_TDM_TDM (1 << 11)
110 #define AUDIO_INTF1_AIFADC_TDM_CHAN0 (0 << 10)
111 #define AUDIO_INTF1_AIFADC_TDM_CHAN1 (1 << 10)
112 #define AUDIO_INTF1_AIF_TRIS (1 << 8)
113 #define AUDIO_INTF1_BCLK_INV (1 << 7)
114 #define AUDIO_INTF1_BCLK_DIR_IN (0 << 6)
115 #define AUDIO_INTF1_BCLK_DIR_OUT (1 << 6)
116 #define AUDIO_INTF1_LRCLK_INV (1 << 6)
117 #define AUDIO_INTF1_WL_16BIT (0 << 2)
118 #define AUDIO_INTF1_WL_20BIT (1 << 2)
119 #define AUDIO_INTF1_WL_24BIT (2 << 2)
120 #define AUDIO_INTF1_WL_32BIT (3 << 2)
121 #define AUDIO_INTF1_FMT_RIGHT (0 << 0)
122 #define AUDIO_INTF1_FMT_LEFT (1 << 0)
123 #define AUDIO_INTF1_FMT_I2S (2 << 0)
124 #define AUDIO_INTF1_FMT_DSP (3 << 0)
125 
126 #define AUDIO_INTF3_LRCLK_DIR_IN (0 << 11)
127 #define AUDIO_INTF3_LRCLK_DIR_OUT (1 << 11)
128 #define AUDIO_INTF3_LRCLK_RATE(x) ((x)&0x7FF)
129 
130 #define DC_SERVO0_ENA_LNR (1 << 3)
131 #define DC_SERVO0_ENA_LNL (1 << 2)
132 #define DC_SERVO0_ENA_HPR (1 << 1)
133 #define DC_SERVO0_ENA_HPL (1 << 0)
134 
135 #define DC_SERVO1_TRIG_1_LNR (1 << 15)
136 #define DC_SERVO1_TRIG_1_LNL (1 << 14)
137 #define DC_SERVO1_TRIG_1_HPR (1 << 13)
138 #define DC_SERVO1_TRIG_1_HPL (1 << 12)
139 #define DC_SERVO1_TRIG_n_LNR (1 << 11)
140 #define DC_SERVO1_TRIG_n_LNL (1 << 10)
141 #define DC_SERVO1_TRIG_n_HPR (1 << 9)
142 #define DC_SERVO1_TRIG_n_HPL (1 << 8)
143 #define DC_SERVO1_TRIG_START_LNR (1 << 7)
144 #define DC_SERVO1_TRIG_START_LNL (1 << 6)
145 #define DC_SERVO1_TRIG_START_HPR (1 << 5)
146 #define DC_SERVO1_TRIG_START_HPL (1 << 4)
147 #define DC_SERVO1_TRIG_DAC_WR_LNR (1 << 3)
148 #define DC_SERVO1_TRIG_DAC_WR_LNL (1 << 2)
149 #define DC_SERVO1_TRIG_DAC_WR_HPR (1 << 1)
150 #define DC_SERVO1_TRIG_DAC_WR_HPL (1 << 0)
151 
152 #define FLL_FRACN_ENA_INT (0 << 2)
153 #define FLL_FRACN_ENA_FRAC (1 << 2)
154 #define FLL_OSC_ENA_DIS (0 << 1)
155 #define FLL_OSC_ENA_EN (1 << 1)
156 #define FLL_ENA_DIS (0 << 0)
157 #define FLL_ENA_EN (1 << 0)
158 
159 #define FLL_OUTDIV(x) ((uint16_t)(((x-1)&0x3F)<<8))
160 #define FLL_CTRL_RATE_FVCO_1 (0 << 4)
161 #define FLL_CTRL_RATE_FVCO_2 (1 << 4)
162 #define FLL_CTRL_RATE_FVCO_3 (2 << 4)
163 #define FLL_CTRL_RATE_FVCO_4 (3 << 4)
164 #define FLL_CTRL_RATE_FVCO_5 (4 << 4)
165 #define FLL_CTRL_RATE_FVCO_6 (5 << 4)
166 #define FLL_CTRL_RATE_FVCO_7 (6 << 4)
167 #define FLL_CTRL_RATE_FVCO_8 (7 << 4)
168 #define FLL_FRATIO_DIV_1 (0 << 0)
169 #define FLL_FRATIO_DIV_2 (1 << 0)
170 #define FLL_FRATIO_DIV_4 (2 << 0)
171 #define FLL_FRATIO_DIV_8 (3 << 0)
172 #define FLL_FRATIO_DIV_16 (7 << 0)
173 
174 #define FLL_K(x) ((uint16_t)(((x)&0xFFFF)<<0))
175 
176 #define FLL_N(x) ((uint16_t)(((x)&0x3FF)<<5))
177 #define FLL_GAIN_1 (0 << 0)
178 #define FLL_GAIN_2 (1 << 0)
179 #define FLL_GAIN_4 (2 << 0)
180 #define FLL_GAIN_8 (3 << 0)
181 #define FLL_GAIN_16 (4 << 0)
182 #define FLL_GAIN_32 (5 << 0)
183 #define FLL_GAIN_64 (6 << 0)
184 #define FLL_GAIN_128 (7 << 0)
185 #define FLL_GAIN_256 (8 << 0)
186 
187 #define FLL_CLK_REF_DIV_1 (0 << 3)
188 #define FLL_CLK_REF_DIV_2 (1 << 3)
189 #define FLL_CLK_REF_DIV_4 (2 << 3)
190 #define FLL_CLK_REF_DIV_8 (3 << 3)
191 #define FLL_CLK_REF_DIV_16 (4 << 3)
192 #define FLL_CLK_REF_SRC_MCLK (0 << 0)
193 #define FLL_CLK_REF_SRC_BCLK (1 << 0)
194 #define FLL_CLK_REF_SRC_LRCLK (2 << 0)
195 
196 
197 #define GPIO_CTL_GPIO_PU (1 << 5)
198 #define GPIO_CTL_GPIO_PD (1 << 4)
199 #define GPIO_CTL_GPIO_IN (0 << 0)
200 #define GPIO_CTL_GPIO_CLK_OUT (1 << 0)
201 #define GPIO_CTL_GPIO_LO (2 << 0)
202 #define GPIO_CTL_GPIO_HI (3 << 0)
203 #define GPIO_CTL_GPIO_IRQ (4 << 0)
204 #define GPIO_CTL_GPIO_FLL_LOCK (5 << 0)
205 #define GPIO_CTL_GPIO_MIC_DET (6 << 0)
206 #define GPIO_CTL_GPIO_MIC_SHORT (7 << 0)
207 #define GPIO_CTL_GPIO_DMIC_CLKO (8 << 0)
208 #define GPIO_CTL_GPIO_FLL_CLKO (9 << 0)
209 
210 #define ANA_IN_MUTE (1 << 7)
211 #define ANA_IN_VOLUME(x) ((uint16_t)(((x)&0x1F) << 0))
212 
213 #define ANA_HP0_HPL_RM_SHORT (1 << 7)
214 #define ANA_HP0_HPL_ENA_OUTP (1 << 6)
215 #define ANA_HP0_HPL_ENA_DLY (1 << 5)
216 #define ANA_HP0_HPL_ENA (1 << 4)
217 #define ANA_HP0_HPR_RM_SHORT (1 << 3)
218 #define ANA_HP0_HPR_ENA_OUTP (1 << 2)
219 #define ANA_HP0_HPR_ENA_DLY (1 << 1)
220 #define ANA_HP0_HPR_ENA (1 << 0)
221 
222 #define ANA_OUT_MUTE (1 << 8)
223 #define ANA_OUT_VOL_UPDATE (1 << 7)
224 #define ANA_OUT_ZERO_CROSS (1 << 6)
225 #define ANA_OUT_VOLUME(x) ((uint16_t)((x&0x3F) << 0))
226 
227 #define DGTL_PULLS_MCLK_PU (1 << 7)
228 #define DGTL_PULLS_MCLK_PD (1 << 6)
229 #define DGTL_PULLS_DACDAT_PU (1 << 5)
230 #define DGTL_PULLS_DACDAT_PD (1 << 4)
231 #define DGTL_PULLS_LRCLK_PU (1 << 3)
232 #define DGTL_PULLS_LRCLK_PD (1 << 2)
233 #define DGTL_PULLS_BCLK_PU (1 << 1)
234 #define DGTL_PULLS_BCLK_PD (1 << 0)
235 
236 #define FLL_NCO_FRC_NCO_EN (1 << 0)
237 #define FLL_NCO_FRC_NCO_DIS (0 << 0)
238 
239 #endif /* ----- #ifndef __WM8904_REG_H ----- */