NetBurner 3.1
nmasic.h
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1 
41 #ifndef _NMASIC_H_
42 #define _NMASIC_H_
43 
45 
46 #define NMI_PERIPH_REG_BASE 0x1000
47 #define NMI_CHIPID (NMI_PERIPH_REG_BASE)
48 #define rNMI_GP_REG_0 (0x149c)
49 #define NMI_GP_REG_1 0x14a0
50 #define CHIP_STATE_REG_COUNT 6
51 
52 #define NMI_VMM_BASE 0x150000
53 #define NMI_VMM_CORE_CFG (NMI_VMM_BASE+0x14)
54 
55 #define WIFI_PERIPH_BASE 0x00000000
56 #define rPA_CONTROL (WIFI_PERIPH_BASE+0x9804)
57 
58 #ifdef CONF_WILC_USE_3000_REV_A
59 #ifdef CONF_WILC_USE_SDIO
60  #define WILC_WAKEUP_REG 0xf0
61  #define WILC_CLK_STATUS_REG 0xf0
62  #define WILC_WAKEUP_BIT NBIT0
63  #define WILC_CLK_STATUS_BIT NBIT4
64  #define WILC_FROM_INTERFACE_TO_WF_REG 0xFA
65  #define WILC_FROM_INTERFACE_TO_WF_BIT NBIT0
66  #define WILC_TO_INTERFACE_FROM_WF_REG 0xFC
67  #define WILC_TO_INTERFACE_FROM_WF_BIT NBIT0
68 
69  #define WILC_INT_STATUS_REG 0xFE
70  #define WILC_INT_CLEAR_REG 0xFE
71 #else
72  #define WILC_WAKEUP_REG 0x1
73  #define WILC_CLK_STATUS_REG 0x13
74  #define WILC_WAKEUP_BIT NBIT1
75  #define WILC_CLK_STATUS_BIT NBIT2
76  #define WILC_FROM_INTERFACE_TO_WF_REG 0x0E
77  #define WILC_FROM_INTERFACE_TO_WF_BIT NBIT0
78  #define WILC_TO_INTERFACE_FROM_WF_REG 0x14
79  #define WILC_TO_INTERFACE_FROM_WF_BIT NBIT0
80 
81  #define WILC_INT_STATUS_REG 0x40
82  #define WILC_INT_CLEAR_REG 0x44
83 
84 #endif /* WILC_SDIO */
85 
86 #elif defined CONF_WILC_USE_1000_REV_B
87 #ifdef CONF_WILC_USE_SDIO
88  #define WILC_WAKEUP_REG 0xf0
89  #define WILC_CLK_STATUS_REG 0xf1
90  #define WILC_WAKEUP_BIT NBIT0
91  #define WILC_CLK_STATUS_BIT NBIT0
92  #define WILC_FROM_INTERFACE_TO_WF_REG 0xFA
93  #define WILC_FROM_INTERFACE_TO_WF_BIT NBIT0
94  #define WILC_TO_INTERFACE_FROM_WF_REG 0xFC
95  #define WILC_TO_INTERFACE_FROM_WF_BIT NBIT0
96 
97  #define WILC_INT_STATUS_REG 0xF7
98  #define WILC_INT_CLEAR_REG 0xF8
99 #else
100  #define WILC_WAKEUP_REG 0x1
101  #define WILC_CLK_STATUS_REG 0xf /* Assume initially it is B0 chip */
102  #define WILC_WAKEUP_BIT NBIT1
103  #define WILC_CLK_STATUS_BIT NBIT2
104 
105  #define WILC_INT_STATUS_REG 0x40
106  #define WILC_INT_CLEAR_REG 0x44
107  #define WILC_FROM_INTERFACE_TO_WF_REG 0x0B
108  #define WILC_FROM_INTERFACE_TO_WF_BIT NBIT0
109  #define WILC_TO_INTERFACE_FROM_WF_REG 0x10
110  #define WILC_TO_INTERFACE_FROM_WF_BIT NBIT0
111 
112 #endif /* WILC_SDIO */
113 #endif /* CONF_WILC_USE_3000_REV_A*/
114 
115 
116 #define NMI_STATE_REG (0x108c)
117 #define NMI_STATE_REG_END (0x149c)
118 #define BOOTROM_REG (0xc000c)
119 #define NMI_REV_REG (0x207ac)
120 #define M2M_WAIT_FOR_HOST_REG (0x207bc)
121 #define M2M_FINISH_INIT_STATE 0x02532636UL
122 #define M2M_FINISH_BOOT_ROM 0x10add09eUL
123 #define M2M_START_FIRMWARE 0xef522f61UL
124 #define M2M_START_PS_FIRMWARE 0x94992610UL
125 
126 #define CHIP_STATE_READY (0b0000)
127 #define CHIP_STATE_FIRM_DL_PASS (0b0001)
128 #define CHIP_STATE_FIRM_DL_FAIL (0b0010)
129 #define CHIP_STATE_ROM_READY (0b0011)
130 #define CHIP_STATE_ROM_TEST_PASS (0b0100)
131 #define CHIP_STATE_ROM_TEST_FIAL (0b0101)
132 #define CHIP_STATE_INIT_FAIL (0b1110)
133 #define CHIP_STATE_INIT_PASS (0b1111)
134 
135 #ifdef CONF_WILC_USE_SPI
136 #define IRG_FLAGS_OFFSET 16
137 #else
138 #define IRG_FLAGS_OFFSET 0
139 #endif
140 
141 #define REV_B0 (0x2B0)
142 #define GET_CHIPID() nmi_get_chipid()
143 #define ISNMC1000(id) (((id & 0xfffff000) == 0x100000) ? 1 : 0)
144 #define ISNMC1500(id) (((id & 0xfffff000) == 0x150000) ? 1 : 0)
145 #define REV(id) ( ((id) & 0x00000fff ) )
146 #define EFUSED_MAC(value) (value & 0xffff0000)
147 
148 #ifdef CONF_WILC_USE_3000_REV_A
149 
150 /* Coexistence Block */
151 #define rCOE_TOP_CTL (WIFI_PERIPH_BASE+0x1124)
152 #define rCOEXIST_CTL (WIFI_PERIPH_BASE+0x161E00)
153 #define rCOEXIST_TIMER (WIFI_PERIPH_BASE+0x161E04)
154 #define rBT_WIRE_SAMPLE_TIME (WIFI_PERIPH_BASE+0x161E08)
155 #define rBT_SLOT_LUMP_CTL1 (WIFI_PERIPH_BASE+0x161E10)
156 #define rBT_CNT_THR (WIFI_PERIPH_BASE+0x161E28)
157 #define rBT_CNT_INT (WIFI_PERIPH_BASE+0x161E78)
158 #define rCOE_AUTO_PS_ON_NULL_PKT (WIFI_PERIPH_BASE+0x160468)
159 #define rCOE_AUTO_PS_OFF_NULL_PKT (WIFI_PERIPH_BASE+0x16046C)
160 #define rTX_ABORT_NULL_FRM_DURATION_TIMEOUT_VALUE (WIFI_PERIPH_BASE+0x16045C)
161 #define rTX_ABORT_NULL_FRM_RATE_POWER_LEVEL (WIFI_PERIPH_BASE+0x160460)
162 #define rTX_ABORT_NULL_FRM_PHY_TX_MODE_SETTING (WIFI_PERIPH_BASE+0x160464)
163 #define rCOE_AUTO_CTS_PKT (WIFI_PERIPH_BASE+0x160470)
164 
165 #define BT_REJECTION_TIMER 0x800
166 #define BT_ACCEPTANCE_TIMER 0x700
167 #define BT_REJ_ACPT_TIMER_TIME_BASE 4
168 #define BT_REG_TIMER_NULL_THRE 0x783 /* Threshold for generating NULL packet enabling wifi power-save mode */
169 #define BT_ACPT_TIMER_THRE 0x000 /* Interrupt will be generated when rej/acc arb counter reach this value */
170 #define COUNT_TO_ONE_US 39 /* Counts to generate 1 microsecond ticks from system clock */
171 
172 #define TX_RATE_1_MBPS 0x0
173 #define TX_RATE_2_MBPS 0x1
174 #define TX_RATE_5_5_MBPS 0x2
175 #define TX_RATE_11_MBPS 0x3
176 #define TX_RATE_6_MBPS 0xb
177 #define TX_RATE_9_MBPS 0xf
178 #define TX_RATE_12_MBPS 0xa
179 #define TX_RATE_18_MBPS 0xe
180 #define TX_RATE_24_MBPS 0x9
181 #define TX_RATE_36_MBPS 0xd
182 #define TX_RATE_48_MBPS 0x8
183 #define TX_RATE_54_MBPS 0xc
184 #define TX_RATE_MCS0_MBPS 0x80
185 #define TX_RATE_MCS1_MBPS 0x81
186 #define TX_RATE_MCS2_MBPS 0x82
187 #define TX_RATE_MCS3_MBPS 0x83
188 #define TX_RATE_MCS4_MBPS 0x84
189 #define TX_RATE_MCS5_MBPS 0x85
190 #define TX_RATE_MCS6_MBPS 0x86
191 #define TX_RATE_MCS7_MBPS 0x87
192 
193 #define PHY_MODE_1_MBPS 0x10141 //802.11b
194 #define PHY_MODE_2_MBPS 0x10141 //802.11b
195 #define PHY_MODE_5_5_MBPS 0x10141 //802.11b
196 #define PHY_MODE_11_MBPS 0x10141 //802.11b
197 #define PHY_MODE_6_MBPS 0x10142 //802.11a
198 #define PHY_MODE_9_MBPS 0x10142 //802.11a
199 #define PHY_MODE_12_MBPS 0x10142 //802.11a
200 #define PHY_MODE_18_MBPS 0x10142 //802.11a
201 #define PHY_MODE_24_MBPS 0x10142 //802.11a
202 #define PHY_MODE_36_MBPS 0x10142 //802.11a
203 #define PHY_MODE_48_MBPS 0x10142 //802.11a
204 #define PHY_MODE_54_MBPS 0x10142 //802.11a
205 #define PHY_MODE_MCS0_MBPS 0x10146 //HT-Mixed
206 #define PHY_MODE_MCS1_MBPS 0x10146 //HT-Mixed
207 #define PHY_MODE_MCS2_MBPS 0x10146 //HT-Mixed
208 #define PHY_MODE_MCS3_MBPS 0x10146 //HT-Mixed
209 #define PHY_MODE_MCS4_MBPS 0x10146 //HT-Mixed
210 #define PHY_MODE_MCS5_MBPS 0x10146 //HT-Mixed
211 #define PHY_MODE_MCS6_MBPS 0x10146 //HT-Mixed
212 #define PHY_MODE_MCS7_MBPS 0x10146 //HT-Mixed
213 #endif
214 
220 typedef struct {
221  uint8 u8FirmwareMajor; /* Version Major Number which represents the official release base */
222  uint8 u8FirmwareMinor; /* Version Minor Number which represents the engineering release base */
223  uint8 u8FirmwarePatch; /* Version pathc Number which represents the pathces release base */
224  uint8 u8DriverMajor; /* Version Major Number which represents the official release base */
225  uint8 u8DriverMinor; /* Version Minor Number which represents the engineering release base */
226  uint8 u8DriverPatch; /* Version Patch Number which represents the pathces release base */
227  uint8 BuildDate[sizeof(__DATE__)];
228  uint8 BuildTime[sizeof(__TIME__)];
229  uint32 u32Chipid; /* HW revision which will be basically the chip ID */
230 } tstrM2mRev;
231 
232 #ifdef __cplusplus
233  extern "C" {
234  #endif
235 
236 
237 sint8 chip_wake(void);
238 /*
239 * @fn chip_sleep
240 * @brief
241 */
242 sint8 chip_sleep(void);
243 void chip_idle(void);
244 
245 
246 sint8 enable_interrupts(void);
247 
248 sint8 cpu_start(void);
249 
250 uint32 nmi_get_chipid(void);
251 
252 uint32 nmi_get_rfrevid(void);
253 
254 void restore_pmu_settings_after_global_reset(void);
255 
256 void nmi_update_pll(void);
257 
258 void nmi_set_sys_clk_src_to_xo(void);
259 
260 sint8 chip_reset(void);
261 
262 sint8 firmware_download(void);
263 
264 #ifdef CONF_WILC_USE_3000_REV_A
265 sint8 cpu_start_bt(void);
266 sint8 firmware_download_bt(void);
267 #endif
268 
269 
270 sint8 wait_for_firmware_start(void);
271 sint8 wait_for_bootrom(void);
272 
273 sint8 chip_deinit(void);
274 
275 sint8 chip_reset_and_cpu_halt(void);
276 
277 sint8 set_gpio_dir(uint8 gpio, uint8 dir);
278 
279 sint8 set_gpio_val(uint8 gpio, uint8 val);
280 
281 sint8 get_gpio_val(uint8 gpio, uint8* val);
282 
283 sint8 pullup_ctrl(uint32 pinmask, uint8 enable);
284 
285 sint8 nmi_get_otp_mac_address(uint8 *pu8MacAddr, uint8 * pu8IsValid);
286 
287 sint8 nmi_get_mac_address(uint8 *pu8MacAddr);
288 
289 #ifdef __cplusplus
290  }
291  #endif
292 
293 #endif /*_NMASIC_H_*/
294 
295 
This module contains common APIs declarations.
signed char sint8
Range of values between -128 to 127.
Definition: nm_bsp.h:123