/* $Revision: 1.1 $ */ /******************************************************************************* * * MCF54418 ColdFire Assembly Header File * Copyright 1998-2010 NetBurner, Inc. ALL RIGHTS RESERVED * * Permission is hereby granted to purchasers of NetBurner hardware to use or * modify this computer program for any use as long as the resultant program is * only executed on NetBurner provided hardware. * * No other rights to use this program or its derivatives in part or in whole * are granted. * * It may be possible to license this or other NetBurner software for use on * non-NetBurner hardware. Please contact licensing@netburner.com for more * information. * * NetBurner makes no representation or warranties with respect to the * performance of this computer program, and specifically disclaims any * responsibility for any damages, special or consequential, connected with use * of this program. * * ---------------------------------------------------------------------------- * * NetBurner, Inc. * 5405 Morehouse Drive * San Diego, CA 92121 * * Information available at: http://www.netburner.com * Support available at: http://support.netburner.com * ******************************************************************************/ #ifndef _SIM54418_H_ #define _SIM54418_H_ typedef volatile unsigned char vubyte; typedef volatile unsigned short vuword; typedef volatile unsigned long vudword; /* * RAPID GPIO */ typedef struct { vuword dir0; /* 0x8C00_0000 -> 0x8C00_0001 - (Read) Data Direction Register (Write) Data Direction Register */ vuword data; /* 0x8C00_0002 -> 0x8C00_0003 - (Read) Write Data Register (Write) Write Data Register */ vuword enb; /* 0x8C00_0004 -> 0x8C00_0005 - (Read) Pin Enable Register (Write) Pin Enable Register */ vuword clr; /* 0x8C00_0006 -> 0x8C00_0007 - (Read) Write Data Register (Write) Write Data Clear Register */ vuword dir1; /* 0x8C00_0008 -> 0x8C00_0009 - (Read) Data Direction Register */ vuword set; /* 0x8C00_000A -> 0x8C00_000B - (Read) Write Data Register (Write) Write Data Set Register */ vuword dir2; /* 0x8C00_000C -> 0x8C00_000D - (Read) Data Direction Register */ vuword tog; /* 0x8C00_000E -> 0x8C00_000F - (Read) Write Data Register (Write) Write Data Toggle Register */ } rgpiostruct; /* * 1-WIRE MODULE */ typedef struct { vubyte cr; /* 0xEC00_8000 -> 0xEC00_8000 - Control Register */ vubyte pack00[3]; /* 0xEC00_8001 -> 0xEC00_8003 - RESERVED */ vubyte div; /* 0xEC00_8004 -> 0xEC00_8004 - Time Divider Register */ vubyte pack01[3]; /* 0xEC00_8005 -> 0xEC00_8007 - RESERVED */ vubyte rst; /* 0xEC00_8008 -> 0xEC00_8008 - Reset Register */ vubyte pack02[3]; /* 0xEC00_8009 -> 0xEC00_800B - RESERVED */ vubyte cmd; /* 0xEC00_800C -> 0xEC00_800C - Command Register */ vubyte pack03[3]; /* 0xEC00_800D -> 0xEC00_800F - RESERVED */ vubyte txrx; /* 0xEC00_8010 -> 0xEC00_8010 - Transmit/Receive Register */ vubyte pack04[3]; /* 0xEC00_8011 -> 0xEC00_8013 - RESERVED */ vubyte isr; /* 0xEC00_8014 -> 0xEC00_8014 - Interrupt Status Register */ vubyte pack05[3]; /* 0xEC00_8015 -> 0xEC00_8017 - RESERVED */ vubyte ier; /* 0xEC00_8018 -> 0xEC00_8018 - Interrupt Enable Register */ vubyte pack06[3]; /* 0xEC00_8019 -> 0xEC00_801B - RESERVED */ } owstruct; /* * I2C MODULE 2-5 (i2c25[4] = 0xEC01_0000 -> 0xEC01_FFFF) */ typedef struct { vubyte i2adr; /* 0x0000 -> 0x0000 - I2C Address Register */ vubyte pack00[3]; /* 0x0001 -> 0x0003 - RESERVED */ vubyte i2fdr; /* 0x0004 -> 0x0004 - I2C Frequency Divider Register */ vubyte pack01[3]; /* 0x0005 -> 0x0007 - RESERVED */ vubyte i2cr; /* 0x0008 -> 0x0008 - I2C Control Register */ vubyte pack02[3]; /* 0x0009 -> 0x000B - RESERVED */ vubyte i2sr; /* 0x000C -> 0x000C - I2C Status Register */ vubyte pack03[3]; /* 0x000D -> 0x000F - RESERVED */ vubyte i2dr; /* 0x0010 -> 0x0010 - I2C Data I/O Register */ vubyte pack04[16367]; /* 0x0011 -> 0x3FFF - RESERVED */ }i2cstruct; //} i2c25struct; // These typedefs are to prevent issues with code that used references to the old // i2c#struct structures, prior to unifying the type definitions. typedef i2cstruct i2c25struct; typedef i2cstruct i2c1struct; typedef i2cstruct i2c0struct; /* * DMA SERIAL PERIPHERAL INTERFACE 2 */ typedef struct { vudword mcr; /* 0xEC03_8000 -> 0xEC03_8003 - Module Configuration Register */ vubyte pack00[4]; /* 0xEC03_8004 -> 0xEC03_8007 - RESERVED */ vudword tcr; /* 0xEC03_8008 -> 0xEC03_800B - Transfer Count Register */ vudword ctar[8]; /* 0xEC03_800C -> 0xEC03_802B - Clock and Transfer Attributes Register 0-7 */ vudword sr; /* 0xEC03_802C -> 0xEC03_802F - Status Register */ vudword rser; /* 0xEC03_8030 -> 0xEC03_8033 - DMA/Interrupt Request Select and Enable Register */ vudword pushr; /* 0xEC03_8034 -> 0xEC03_8037 - Push Tx FIFO Register */ vudword popr; /* 0xEC03_8038 -> 0xEC03_803B - Pop Rx FIFO Register */ vudword txfr[16]; /* 0xEC03_803C -> 0xEC03_807B - Transmit FIFO Register 0-15 */ vudword rxfr[16]; /* 0xEC03_807C -> 0xEC03_80BB - Receive FIFO Register 0-15 */ } dspistruct; //} dspi2struct; // These typedefs are to prevent issues with code that used references to the old // dspi#struct structures, prior to unifying the type definitions. typedef dspistruct dspi0struct; typedef dspistruct dspi1struct; typedef dspistruct dspi2struct; typedef dspistruct dspi3struct; /* * DMA SERIAL PERIPHERAL INTERFACE 3 */ //typedef struct { // vudword mcr; /* 0xEC03_C000 -> 0xEC03_C003 - Module Configuration Register */ // vubyte pack00[4]; /* 0xEC03_C004 -> 0xEC03_C007 - RESERVED */ // vudword tcr; /* 0xEC03_C008 -> 0xEC03_C00B - Transfer Count Register */ // vudword ctar[8]; /* 0xEC03_C00C -> 0xEC03_C02B - Clock and Transfer Attributes Register 0-7 */ // vudword sr; /* 0xEC03_C02C -> 0xEC03_C02F - Status Register */ // vudword rser; /* 0xEC03_C030 -> 0xEC03_C033 - DMA/Interrupt Request Select and Enable Register */ // vudword pushr; /* 0xEC03_C034 -> 0xEC03_C037 - Push Tx FIFO Register */ // vudword popr; /* 0xEC03_C038 -> 0xEC03_C03B - Pop Rx FIFO Register */ // vudword txfr[16]; /* 0xEC03_C03C -> 0xEC03_C07B - Transmit FIFO Register 0-15 */ // vudword rxfr[16]; /* 0xEC03_C07C -> 0xEC03_C0BB - Receive FIFO Register 0-15 */ //} dspi3struct; /* * UART MODULE 4-9 (uarts[6] = 0xEC06_0000 -> 0xEC07_7FFF) * Same as uartstruct. */ /* * MOTOR CONTROL PULSE-WIDTH MODULATOR SUBMODULE 0-3 (sm[4] = 0xEC08_8000 -> 0xEC08_813F) */ typedef struct { vuword cnt; /* 0x00 -> 0x01 - Counter Register */ vuword init; /* 0x02 -> 0x03 - Initial Count Register */ vuword cr2; /* 0x04 -> 0x05 - Control Register 2 */ vuword cr1; /* 0x06 -> 0x07 - Control Register 1 */ vuword val[6]; /* 0x08 -> 0x13 - Value Register 0-5 */ vubyte pack00[4]; /* 0x14 -> 0x17 - RESERVED */ vuword ocr; /* 0x18 -> 0x19 - Output Control Register */ vuword sr; /* 0x1A -> 0x1B - Status Register */ vuword ier; /* 0x1C -> 0x1D - Interrupt Enable Register */ vuword dmaen; /* 0x1E -> 0x1F - DMA Enable Register */ vuword otcr; /* 0x20 -> 0x21 - Output Trigger Control Register */ vuword dismap; /* 0x22 -> 0x23 - Fault Disable Mapping Register */ vuword dtcnt0; /* 0x24 -> 0x25 - Deadtime Count Register 0 */ vuword dtcnt1; /* 0x26 -> 0x27 - Deadtime Count Register 1 */ vuword ccra; /* 0x28 -> 0x29 - Capture Control Register A */ vuword ccmpa; /* 0x2A -> 0x2B - Capture Compare Register A */ vuword ccrb; /* 0x2C -> 0x2D - Capture Control Register B */ vuword ccmpb; /* 0x2E -> 0x2F - Capture Compare Register B */ vuword ccrx; /* 0x30 -> 0x31 - Capture Control Register X */ vuword ccmpx; /* 0x32 -> 0x33 - Capture Compare Register X */ vuword cval0; /* 0x34 -> 0x35 - Capture Value 0 Register */ vuword ccyc0; /* 0x36 -> 0x37 - Capture Value 0 Cycle Register */ vuword cval1; /* 0x38 -> 0x39 - Capture Value 1 Register */ vuword ccyc1; /* 0x3A -> 0x3B - Capture Value 1 Cycle Register */ vuword cval2; /* 0x3C -> 0x3D - Capture Value 2 Register */ vuword ccyc2; /* 0x3E -> 0x3F - Capture Value 2 Cycle Register */ vuword cval3; /* 0x40 -> 0x41 - Capture Value 3 Register */ vuword ccyc3; /* 0x42 -> 0x43 - Capture Value 3 Cycle Register */ vuword cval4; /* 0x44 -> 0x45 - Capture Value 4 Register */ vuword ccyc4; /* 0x46 -> 0x47 - Capture Value 4 Cycle Register */ vuword cval5; /* 0x48 -> 0x49 - Capture Value 5 Register */ vuword ccyc5; /* 0x4A -> 0x4B - Capture Value 5 Cycle Register */ vubyte pack01[4]; /* 0x4C -> 0x4F - RESERVED */ } mcpwm_smstruct; /* * MOTOR CONTROL PULSE-WIDTH MODULATOR */ typedef struct { mcpwm_smstruct sm[4]; /* 0xEC08_8000 -> 0xEC08_813F - Submodule 0-3 */ vuword outen; /* 0xEC08_8140 -> 0xEC08_8141 - Output Enable Register */ vuword mask; /* 0xEC08_8142 -> 0xEC08_8143 - Output Mask Register */ vuword swcout; /* 0xEC08_8144 -> 0xEC08_8145 - Software Controlled Output Register */ vuword dtss; /* 0xEC08_8146 -> 0xEC08_8147 - Deadtime Source Select Register */ vuword mcr; /* 0xEC08_8148 -> 0xEC08_8149 - Master Control Register */ vubyte pack00[2]; /* 0xEC08_814A -> 0xEC08_814B - RESERVED */ vuword fcr; /* 0xEC08_814C -> 0xEC08_814D - Fault Control Register */ vuword fsr; /* 0xEC08_814E -> 0xEC08_814F - Fault Status Register */ vuword ffilt; /* 0xEC08_8150 -> 0xEC08_8151 - Fault Filter Register */ vubyte pack01[2]; /* 0xEC08_8152 -> 0xEC08_8153 - RESERVED */ } mcpwmstruct; /* * RESET CONTROLLER */ typedef struct { vubyte rcr; /* 0xEC09_0000 -> 0xEC09_0000 - Reset Control Register */ vubyte rsr; /* 0xEC09_0001 -> 0xEC09_0001 - Reset Status Register */ vubyte pack00[2]; /* 0xEC09_0002 -> 0xEC09_0003 - RESERVED */ } resetstruct; /* * CHIP CONFIGURATION MODULE */ typedef struct { vuword ccr; /* 0xEC09_0004 -> 0xEC09_0005 - Chip Configuration Register */ vubyte pack00; /* 0xEC09_0006 -> 0xEC09_0006 - RESERVED */ vubyte lpcr; /* 0xEC09_0007 -> 0xEC09_0007 - Low-Power Control Register */ vuword rcon; /* 0xEC09_0008 -> 0xEC09_0009 - Reset Configuration Register */ vuword cir; /* 0xEC09_000A -> 0xEC09_000B - Chip Identification Register */ vubyte pack01[2]; /* 0xEC09_000C -> 0xEC09_000D - RESERVED */ vuword misccr; /* 0xEC09_000E -> 0xEC09_000F - Miscellaneous Control Register */ vuword cdrh; /* 0xEC09_0010 -> 0xEC09_0011 - Clock Divider Register High */ vuword cdrl; /* 0xEC09_0012 -> 0xEC09_0013 - Clock Divider Register Low */ vuword uocsr; /* 0xEC09_0014 -> 0xEC09_0015 - USB On-the-Go Controller Status Register */ vuword uhcsr; /* 0xEC09_0016 -> 0xEC09_0017 - USB Host Controller Status Register */ vuword misccr3; /* 0xEC09_0018 -> 0xEC09_0019 - Miscellaneous Control Register 3 */ vuword misccr2; /* 0xEC09_001A -> 0xEC09_001B - Miscellaneous Control Register 2 */ vuword adctsr; /* 0xEC09_001C -> 0xEC09_001D - ADC Trigger Select Register */ vuword dactsr; /* 0xEC09_001E -> 0xEC09_001F - DAC Trigger Select Register */ vuword sbfsr; /* 0xEC09_0020 -> 0xEC09_0021 - Serial Boot Facility Status Register */ vuword sbfcr; /* 0xEC09_0022 -> 0xEC09_0023 - Serial Boot Facility Control Register */ vudword fnacr; /* 0xEC09_0024 -> 0xEC09_0027 - FlexBus/NAND Flash Arbiter Control Register */ } ccmstruct; /* * PIN-MULTIPLEXING AND CONTROL (GPIO) */ typedef struct { vubyte podr_a; /* 0xEC09_4000 -> 0xEC09_4000 - Port Output Data Register A */ vubyte podr_b; /* 0xEC09_4001 -> 0xEC09_4001 - Port Output Data Register B */ vubyte podr_c; /* 0xEC09_4002 -> 0xEC09_4002 - Port Output Data Register C */ vubyte podr_d; /* 0xEC09_4003 -> 0xEC09_4003 - Port Output Data Register D */ vubyte podr_e; /* 0xEC09_4004 -> 0xEC09_4004 - Port Output Data Register E */ vubyte podr_f; /* 0xEC09_4005 -> 0xEC09_4005 - Port Output Data Register F */ vubyte podr_g; /* 0xEC09_4006 -> 0xEC09_4006 - Port Output Data Register G */ vubyte podr_h; /* 0xEC09_4007 -> 0xEC09_4007 - Port Output Data Register H */ vubyte podr_i; /* 0xEC09_4008 -> 0xEC09_4008 - Port Output Data Register I */ vubyte podr_j; /* 0xEC09_4009 -> 0xEC09_4009 - Port Output Data Register J */ vubyte podr_k; /* 0xEC09_400A -> 0xEC09_400A - Port Output Data Register K */ vubyte pack00; /* 0xEC09_400B -> 0xEC09_400B - RESERVED */ vubyte pddr_a; /* 0xEC09_400C -> 0xEC09_400C - Port Data Direction Register A */ vubyte pddr_b; /* 0xEC09_400D -> 0xEC09_400D - Port Data Direction Register B */ vubyte pddr_c; /* 0xEC09_400E -> 0xEC09_400E - Port Data Direction Register C */ vubyte pddr_d; /* 0xEC09_400F -> 0xEC09_400F - Port Data Direction Register D */ vubyte pddr_e; /* 0xEC09_4010 -> 0xEC09_4010 - Port Data Direction Register E */ vubyte pddr_f; /* 0xEC09_4011 -> 0xEC09_4011 - Port Data Direction Register F */ vubyte pddr_g; /* 0xEC09_4012 -> 0xEC09_4012 - Port Data Direction Register G */ vubyte pddr_h; /* 0xEC09_4013 -> 0xEC09_4013 - Port Data Direction Register H */ vubyte pddr_i; /* 0xEC09_4014 -> 0xEC09_4014 - Port Data Direction Register I */ vubyte pddr_j; /* 0xEC09_4015 -> 0xEC09_4015 - Port Data Direction Register J */ vubyte pddr_k; /* 0xEC09_4016 -> 0xEC09_4016 - Port Data Direction Register K */ vubyte pack01; /* 0xEC09_4017 -> 0xEC09_4017 - RESERVED */ vubyte ppdsdr_a; /* 0xEC09_4018 -> 0xEC09_4018 - Port Pin Data/Set Data Register A */ vubyte ppdsdr_b; /* 0xEC09_4019 -> 0xEC09_4019 - Port Pin Data/Set Data Register B */ vubyte ppdsdr_c; /* 0xEC09_401A -> 0xEC09_401A - Port Pin Data/Set Data Register C */ vubyte ppdsdr_d; /* 0xEC09_401B -> 0xEC09_401B - Port Pin Data/Set Data Register D */ vubyte ppdsdr_e; /* 0xEC09_401C -> 0xEC09_401C - Port Pin Data/Set Data Register E */ vubyte ppdsdr_f; /* 0xEC09_401D -> 0xEC09_401D - Port Pin Data/Set Data Register F */ vubyte ppdsdr_g; /* 0xEC09_401E -> 0xEC09_401E - Port Pin Data/Set Data Register G */ vubyte ppdsdr_h; /* 0xEC09_401F -> 0xEC09_401F - Port Pin Data/Set Data Register H */ vubyte ppdsdr_i; /* 0xEC09_4020 -> 0xEC09_4020 - Port Pin Data/Set Data Register I */ vubyte ppdsdr_j; /* 0xEC09_4021 -> 0xEC09_4021 - Port Pin Data/Set Data Register J */ vubyte ppdsdr_k; /* 0xEC09_4022 -> 0xEC09_4022 - Port Pin Data/Set Data Register K */ vubyte pack02; /* 0xEC09_4023 -> 0xEC09_4023 - RESERVED */ vubyte pclrr_a; /* 0xEC09_4024 -> 0xEC09_4024 - Port Clear Output Data Register A */ vubyte pclrr_b; /* 0xEC09_4025 -> 0xEC09_4025 - Port Clear Output Data Register B */ vubyte pclrr_c; /* 0xEC09_4026 -> 0xEC09_4026 - Port Clear Output Data Register C */ vubyte pclrr_d; /* 0xEC09_4027 -> 0xEC09_4027 - Port Clear Output Data Register D */ vubyte pclrr_e; /* 0xEC09_4028 -> 0xEC09_4028 - Port Clear Output Data Register E */ vubyte pclrr_f; /* 0xEC09_4029 -> 0xEC09_4029 - Port Clear Output Data Register F */ vubyte pclrr_g; /* 0xEC09_402A -> 0xEC09_402A - Port Clear Output Data Register G */ vubyte pclrr_h; /* 0xEC09_402B -> 0xEC09_402B - Port Clear Output Data Register H */ vubyte pclrr_i; /* 0xEC09_402C -> 0xEC09_402C - Port Clear Output Data Register I */ vubyte pclrr_j; /* 0xEC09_402D -> 0xEC09_402D - Port Clear Output Data Register J */ vubyte pclrr_k; /* 0xEC09_402E -> 0xEC09_402E - Port Clear Output Data Register K */ vubyte pack03; /* 0xEC09_402F -> 0xEC09_402F - RESERVED */ vuword pcr_a; /* 0xEC09_4030 -> 0xEC09_4031 - Pull Control Register A */ vuword pcr_b; /* 0xEC09_4032 -> 0xEC09_4033 - Pull Control Register B */ vuword pcr_c; /* 0xEC09_4034 -> 0xEC09_4035 - Pull Control Register C */ vuword pcr_d; /* 0xEC09_4036 -> 0xEC09_4037 - Pull Control Register D */ vuword pcr_e; /* 0xEC09_4038 -> 0xEC09_4039 - Pull Control Register E */ vuword pcr_f; /* 0xEC09_403A -> 0xEC09_403B - Pull Control Register F */ vuword pcr_g; /* 0xEC09_403C -> 0xEC09_403D - Pull Control Register G */ vuword pcr_h; /* 0xEC09_403E -> 0xEC09_403F - Pull Control Register H */ vuword pcr_i; /* 0xEC09_4040 -> 0xEC09_4041 - Pull Control Register I */ vuword pcr_j; /* 0xEC09_4042 -> 0xEC09_4043 - Pull Control Register J */ vuword pcr_k; /* 0xEC09_4044 -> 0xEC09_4045 - Pull Control Register K */ vubyte pack04[2]; /* 0xEC09_4046 -> 0xEC09_4047 - RESERVED */ vubyte par_fbctl; /* 0xEC09_4048 -> 0xEC09_4048 - Pin Assignment Register - FlexBus Control */ vubyte par_be; /* 0xEC09_4049 -> 0xEC09_4049 - Pin Assignment Register - Byte Enable */ vubyte par_cs; /* 0xEC09_404A -> 0xEC09_404A - Pin Assignment Register - Chip Select */ vubyte par_cani2c; /* 0xEC09_404B -> 0xEC09_404B - Pin Assignment Register - CAN1 and I2C0 */ vubyte par_irq0h; /* 0xEC09_404C -> 0xEC09_404C - Pin Assignment Register - Edge Port 0 High */ vubyte par_irq0l; /* 0xEC09_404D -> 0xEC09_404D - Pin Assignment Register - Edge Port 0 Low */ vubyte par_dspiowh; /* 0xEC09_404E -> 0xEC09_404E - Pin Assignment Register - DSPI0 and One-Wire High */ vubyte par_dspiowl; /* 0xEC09_404F -> 0xEC09_404F - Pin Assignment Register - DSPI0 and One-Wire Low */ vubyte par_timer; /* 0xEC09_4050 -> 0xEC09_4050 - Pin Assignment Register - Timer */ vubyte par_uart2; /* 0xEC09_4051 -> 0xEC09_4051 - Pin Assignment Register - UART 2 */ vubyte par_uart1; /* 0xEC09_4052 -> 0xEC09_4052 - Pin Assignment Register - UART 1 */ vubyte par_uart0; /* 0xEC09_4053 -> 0xEC09_4053 - Pin Assignment Register - UART 0 */ vubyte par_sdhch; /* 0xEC09_4054 -> 0xEC09_4054 - Pin Assignment Register - eSDHC High */ vubyte par_sdhcl; /* 0xEC09_4055 -> 0xEC09_4055 - Pin Assignment Register - eSDHC Low */ vubyte par_simp0h; /* 0xEC09_4056 -> 0xEC09_4056 - Pin Assignment Register - SIM Port 0 High */ vubyte par_simp0l; /* 0xEC09_4057 -> 0xEC09_4057 - Pin Assignment Register - SIM Port 0 Low */ vubyte par_ssi0h; /* 0xEC09_4058 -> 0xEC09_4058 - Pin Assignment Register - SSI0 High */ vubyte par_ssi0l; /* 0xEC09_4059 -> 0xEC09_4059 - Pin Assignment Register - SSI0 Low */ vubyte par_debugh1; /* 0xEC09_405A -> 0xEC09_405A - Pin Assignment Register - Debug High 1 */ vubyte par_debugh0; /* 0xEC09_405B -> 0xEC09_405B - Pin Assignment Register - Debug High 0 */ vubyte par_debugl; /* 0xEC09_405C -> 0xEC09_405C - Pin Assignment Register - Debug Low */ vubyte pack05; /* 0xEC09_405D -> 0xEC09_405D - RESERVED */ vubyte par_fec; /* 0xEC09_405E -> 0xEC09_405E - Pin Assignment Register - Fast Ethernet Channel */ vubyte pack06; /* 0xEC09_405F -> 0xEC09_405F - RESERVED */ vubyte mscr_sdramc; /* 0xEC09_4060 -> 0xEC09_4060 - Mode Select Control Register - SDRAM Controller */ vubyte pack07[3]; /* 0xEC09_4061 -> 0xEC09_4063 - RESERVED */ vubyte srcr_fb1; /* 0xEC09_4064 -> 0xEC09_4064 - Slew Rate Control Register - FlexBus 1 */ vubyte srcr_fb2; /* 0xEC09_4065 -> 0xEC09_4065 - Slew Rate Control Register - FlexBus 2 */ vubyte srcr_fb3; /* 0xEC09_4066 -> 0xEC09_4066 - Slew Rate Control Register - FlexBus 3 */ vubyte srcr_fb4; /* 0xEC09_4067 -> 0xEC09_4067 - Slew Rate Control Register - FlexBus 4 */ vubyte srcr_dspiow; /* 0xEC09_4068 -> 0xEC09_4068 - Slew Rate Control Register - DSPI0 and One-Wire */ vubyte srcr_cani2c; /* 0xEC09_4069 -> 0xEC09_4069 - Slew Rate Control Register - CAN1 and I2C0 */ vubyte srcr_irq0; /* 0xEC09_406A -> 0xEC09_406A - Slew Rate Control Register - Edge Port 0 */ vubyte srcr_timer; /* 0xEC09_406B -> 0xEC09_406B - Slew Rate Control Register - Timer */ vubyte srcr_uart; /* 0xEC09_406C -> 0xEC09_406C - Slew Rate Control Register - UART */ vubyte srcr_fec; /* 0xEC09_406D -> 0xEC09_406D - Slew Rate Control Register - Fast Ethernet Channel */ vubyte srcr_sdhc; /* 0xEC09_406E -> 0xEC09_406E - Slew Rate Control Register - eSDHC */ vubyte srcr_simp0; /* 0xEC09_406F -> 0xEC09_406F - Slew Rate Control Register - SIM Port 0 */ vubyte srcr_ssi0; /* 0xEC09_4070 -> 0xEC09_4070 - Slew Rate Control Register - SSI0 */ vubyte pack08[3]; /* 0xEC09_4071 -> 0xEC09_4073 - RESERVED */ vuword urts_pol; /* 0xEC09_4074 -> 0xEC09_4075 - Miscellaneous UART Register - RTS Polarity Control */ vuword ucts_pol; /* 0xEC09_4076 -> 0xEC09_4077 - Miscellaneous UART Register - CTS Polarity Control */ vuword utxd_wom; /* 0xEC09_4078 -> 0xEC09_4079 - Miscellaneous UART Register - Tx Wired-Or Mode Control */ vubyte pack09[2]; /* 0xEC09_407A -> 0xEC09_407B - RESERVED */ vudword urxd_wom; /* 0xEC09_407C -> 0xEC09_407F - Miscellaneous UART Register - Rx Wired-Or Mode Control */ vudword hcr1; /* 0xEC09_4080 -> 0xEC09_4083 - Hysteresis Control Register 1 */ vudword hcr0; /* 0xEC09_4084 -> 0xEC09_4087 - Hysteresis Control Register 0 */ } gpiostruct; /* * CROSSBAR SWITCH (XBS) */ typedef struct { vudword prs0; /* 0xFC00_4000 -> 0xFC00_4003 - Priority Register Slave 0 */ vubyte pack00[12]; /* 0xFC00_4004 -> 0xFC00_400F - RESERVED */ vudword crs0; /* 0xFC00_4010 -> 0xFC00_4013 - Control Register Slave 0 */ vubyte pack01[236]; /* 0xFC00_4014 -> 0xFC00_40FF - RESERVED */ vudword prs1; /* 0xFC00_4100 -> 0xFC00_4103 - Priority Register Slave 1 */ vubyte pack02[12]; /* 0xFC00_4104 -> 0xFC00_410F - RESERVED */ vudword crs1; /* 0xFC00_4110 -> 0xFC00_4113 - Control Register Slave 1 */ vubyte pack03[236]; /* 0xFC00_4114 -> 0xFC00_41FF - RESERVED */ vudword prs2; /* 0xFC00_4200 -> 0xFC00_4203 - Priority Register Slave 2 */ vubyte pack04[12]; /* 0xFC00_4204 -> 0xFC00_420F - RESERVED */ vudword crs2; /* 0xFC00_4210 -> 0xFC00_4213 - Control Register Slave 2 */ vubyte pack05[492]; /* 0xFC00_4214 -> 0xFC00_43FF - RESERVED */ vudword prs4; /* 0xFC00_4400 -> 0xFC00_4403 - Priority Register Slave 4 */ vubyte pack06[12]; /* 0xFC00_4404 -> 0xFC00_440F - RESERVED */ vudword crs4; /* 0xFC00_4410 -> 0xFC00_4413 - Control Register Slave 4 */ vubyte pack07[492]; /* 0xFC00_4414 -> 0xFC00_45FF - RESERVED */ vudword prs6; /* 0xFC00_4600 -> 0xFC00_4603 - Priority Register Slave 6 */ vubyte pack08[12]; /* 0xFC00_4604 -> 0xFC00_460F - RESERVED */ vudword crs6; /* 0xFC00_4610 -> 0xFC00_4613 - Control Register Slave 6 */ vubyte pack09[236]; /* 0xFC00_4614 -> 0xFC00_46FF - RESERVED */ vudword prs7; /* 0xFC00_4700 -> 0xFC00_4703 - Priority Register Slave 7 */ vubyte pack10[12]; /* 0xFC00_4704 -> 0xFC00_470F - RESERVED */ vudword crs7; /* 0xFC00_4710 -> 0xFC00_4713 - Control Register Slave 7 */ } xbsstruct; /* * CHIP SELECT 0-5 (cs[6] = 0xFC00_8000 -> 0xFC00_8047) */ typedef struct { vudword csar; /* 0x0000 -> 0x0003 - Chip Select Address Register */ vudword csmr; /* 0x0004 -> 0x0007 - Chip Select Mask Register */ vudword cscr; /* 0x0008 -> 0x000B - Chip Select Control Register */ } csstruct; /* * CONTROLLER AREA NETWORK MESSAGE BUFFER */ typedef struct { vuword bStatus; /* 0x00 -> 0x01 - Code[11:8]; SRR[6]; IDE[5]; RTR[4]; Length[3:0] */ vuword bTimeStamp; /* 0x02 -> 0x03 - Time Stamp */ vudword id; /* 0x04 -> 0x07 - Standard ID[28:18]; Extended ID[17:0] */ vubyte data[8]; /* 0x08 -> 0x0F - Data Bytes 0-7 */ } can_mbstruct; /* * CONTROLLER AREA NETWORK (FLEXCAN) 0-1 (can[2] = 0xFC02_0000 -> 0xFC02_7FFF) */ typedef struct { vudword canmcr; /* 0x0000 -> 0x0003 - Module Configuration Register */ vudword canctrl; /* 0x0004 -> 0x0007 - Control Register */ vudword timer; /* 0x0008 -> 0x000B - Free Running Timer */ vubyte pack00[4]; /* 0x000C -> 0x000F - RESERVED */ vudword rxgmask; /* 0x0010 -> 0x0013 - Rx Global Mask */ vudword rx14mask; /* 0x0014 -> 0x0017 - Rx Buffer 14 Mask */ vudword rx15mask; /* 0x0018 -> 0x001B - Rx Buffer 15 Mask */ vudword errcnt; /* 0x001C -> 0x001F - Error Counter Register */ vudword errstat; /* 0x0020 -> 0x0023 - Error and Status Register */ vubyte pack01[4]; /* 0x0024 -> 0x0027 - RESERVED */ vudword imask; /* 0x0028 -> 0x002B - Interrupt Mask Register */ vubyte pack02[4]; /* 0x002C -> 0x002F - RESERVED */ vudword iflag; /* 0x0030 -> 0x0033 - Interrupt Flag Register */ vubyte pack03[76]; /* 0x0034 -> 0x007F - RESERVED */ can_mbstruct mbs[16]; /* 0x0080 -> 0x017F - Message Buffers 0-15 */ vubyte pack04[1792]; /* 0x0180 -> 0x087F - RESERVED */ vudword rximr[16]; /* 0x0880 -> 0x08BF - Rx Individual Mask Registers 0-15 */ vubyte pack05[14144]; /* 0x08C0 -> 0x3FFF - RESERVED */ } canstruct; /* * I2C MODULE 1 */ //typedef struct { // vubyte i2adr; /* 0xFC03_8000 -> 0xFC03_8000 - I2C Address Register */ // vubyte pack00[3]; /* 0xFC03_8001 -> 0xFC03_8003 - RESERVED */ // vubyte i2fdr; /* 0xFC03_8004 -> 0xFC03_8004 - I2C Frequency Divider Register */ // vubyte pack01[3]; /* 0xFC03_8005 -> 0xFC03_8007 - RESERVED */ // vubyte i2cr; /* 0xFC03_8008 -> 0xFC03_8008 - I2C Control Register */ // vubyte pack02[3]; /* 0xFC03_8009 -> 0xFC03_800B - RESERVED */ // vubyte i2sr; /* 0xFC03_800C -> 0xFC03_800C - I2C Status Register */ // vubyte pack03[3]; /* 0xFC03_800D -> 0xFC03_800F - RESERVED */ // vubyte i2dr; /* 0xFC03_8010 -> 0xFC03_8010 - I2C Data I/O Register */ // vubyte pack04[3]; /* 0xFC03_8011 -> 0xFC03_8013 - RESERVED */ //} i2c1struct; /* * DMA SERIAL PERIPHERAL INTERFACE 1 */ //typedef struct { // vudword mcr; /* 0xFC03_C000 -> 0xFC03_C003 - Module Configuration Register */ // vubyte pack00[4]; /* 0xFC03_C004 -> 0xFC03_C007 - RESERVED */ // vudword tcr; /* 0xFC03_C008 -> 0xFC03_C00B - Transfer Count Register */ // vudword ctar[8]; /* 0xFC03_C00C -> 0xFC03_C02B - Clock and Transfer Attributes Register 0-7 */ // vudword sr; /* 0xFC03_C02C -> 0xFC03_C02F - Status Register */ // vudword rser; /* 0xFC03_C030 -> 0xFC03_C033 - DMA/Interrupt Request Select and Enable Register */ // vudword pushr; /* 0xFC03_C034 -> 0xFC03_C037 - Push Tx FIFO Register */ // vudword popr; /* 0xFC03_C038 -> 0xFC03_C03B - Pop Rx FIFO Register */ // vudword txfr[16]; /* 0xFC03_C03C -> 0xFC03_C07B - Transmit FIFO Register 0-15 */ // vudword rxfr[16]; /* 0xFC03_C07C -> 0xFC03_C0BB - Receive FIFO Register 0-15 */ //} dspi1struct; /* * SYSTEM CONTROL MODULE AND POWER MANAGEMENT */ typedef struct { vubyte pack00[3]; /* 0xFC04_0010 -> 0xFC04_0012 - RESERVED */ vubyte wcr; /* 0xFC04_0013 -> 0xFC04_0013 - Wakeup Control Register */ vubyte pack01[2]; /* 0xFC04_0014 -> 0xFC04_0015 - RESERVED */ vuword cwcr; /* 0xFC04_0016 -> 0xFC04_0017 - Core Watchdog Control Register */ vubyte pack02[3]; /* 0xFC04_0018 -> 0xFC04_001A - RESERVED */ vubyte cwsr; /* 0xFC04_001B -> 0xFC04_001B - Core Watchdog Service Register */ vubyte pack03[3]; /* 0xFC04_001C -> 0xFC04_001E - RESERVED */ vubyte scmisr; /* 0xFC04_001F -> 0xFC04_001F - SCM Interrupt Status Register */ vubyte pack04[4]; /* 0xFC04_0020 -> 0xFC04_0023 - RESERVED */ vudword bcr; /* 0xFC04_0024 -> 0xFC04_0027 - Burst Configuration Register */ vubyte pack05[4]; /* 0xFC04_0028 -> 0xFC04_002B - RESERVED */ vubyte ppmsr0; /* 0xFC04_002C -> 0xFC04_002C - Peripheral Power Management Set Register 0 */ vubyte ppmcr0; /* 0xFC04_002D -> 0xFC04_002D - Peripheral Power Management Clear Register 0 */ vubyte ppmsr1; /* 0xFC04_002E -> 0xFC04_002E - Peripheral Power Management Set Register 1 */ vubyte ppmcr1; /* 0xFC04_002F -> 0xFC04_002F - Peripheral Power Management Clear Register 1 */ vudword ppmhr0; /* 0xFC04_0030 -> 0xFC04_0033 - Peripheral Power Management High Register 0 */ vudword ppmlr0; /* 0xFC04_0034 -> 0xFC04_0037 - Peripheral Power Management Low Register 0 */ vudword ppmhr1; /* 0xFC04_0038 -> 0xFC04_003B - Peripheral Power Management High Register 1 */ vudword ppmlr1; /* 0xFC04_003C -> 0xFC04_003F - Peripheral Power Management Low Register 1 */ vubyte pack06[48]; /* 0xFC04_0040 -> 0xFC04_006F - RESERVED */ vudword cfadr; /* 0xFC04_0070 -> 0xFC04_0073 - Core Fault Address Register */ vubyte pack07; /* 0xFC04_0074 -> 0xFC04_0074 - RESERVED */ vubyte cfier; /* 0xFC04_0075 -> 0xFC04_0075 - Core Fault Interrupt Enable Register */ vubyte cfloc; /* 0xFC04_0076 -> 0xFC04_0076 - Core Fault Location Register */ vubyte cfatr; /* 0xFC04_0077 -> 0xFC04_0077 - Core Fault Attributes Register */ vubyte pack08[4]; /* 0xFC04_0078 -> 0xFC04_007B - RESERVED */ vudword cfdtr; /* 0xFC04_007C -> 0xFC04_007F - Core Fault Data Register */ } scmstruct; /* * EDMA TRANSFER CONTROL DESCRIPTOR (tcd[16] = 0xFC04_5000 -> 0xFC04_51FF) */ typedef struct { vudword saddr; /* 0x0000 -> 0x0003 - Source Address */ vuword attr; /* 0x0004 -> 0x0005 - Transfer Attributes */ vuword soff; /* 0x0006 -> 0x0007 - Signed Source Address Offset */ vudword nbytes; /* 0x0008 -> 0x000B - Signed Minor Loop Offset/Minor Byte Count */ vudword slast; /* 0x000C -> 0x000F - Last Source Address Adjustment */ vudword daddr; /* 0x0010 -> 0x0013 - Destination Address */ vuword citer; /* 0x0014 -> 0x0015 - Current Minor Loop Link/Major Loop Count */ vuword doff; /* 0x0016 -> 0x0017 - Signed Destination Address Offset */ vudword dlast_sga; /* 0x0018 -> 0x001B - Last Destination Addr. Adjustment/Scatter Gather Addr. */ vuword biter; /* 0x001C -> 0x001D - Beginning Minor Loop Link/Major Loop Count */ vuword csr; /* 0x001E -> 0x001F - Control and Status */ } edma_tcdstruct; /* * ENHANCED DIRECT MEMORY ACCESS (EDMA) CONTROLLER */ typedef struct { vudword cr; /* 0xFC04_4000 -> 0xFC04_4003 - eDMA Control Register */ vudword es; /* 0xFC04_4004 -> 0xFC04_4007 - eDMA Error Status Register */ vudword erqh; /* 0xFC04_4008 -> 0xFC04_400B - eDMA Enable Request High Register */ vudword erql; /* 0xFC04_400C -> 0xFC04_400F - eDMA Enable Request Register */ vudword eeih; /* 0xFC04_4010 -> 0xFC04_4013 - eDMA Enable Error Interrupt High Register */ vudword eeil; /* 0xFC04_4014 -> 0xFC04_4017 - eDMA Enable Error Interrupt Low Register */ vubyte serq; /* 0xFC04_4018 -> 0xFC04_4018 - eDMA Set Enable Request */ vubyte cerq; /* 0xFC04_4019 -> 0xFC04_4019 - eDMA Clear Enable Request */ vubyte seei; /* 0xFC04_401A -> 0xFC04_401A - eDMA Set Enable Error Interrupt Register */ vubyte ceei; /* 0xFC04_401B -> 0xFC04_401B - eDMA Clear Enable Error Interrupt Register */ vubyte cint; /* 0xFC04_401C -> 0xFC04_401C - eDMA Clear Interrupt Request Register */ vubyte cerr; /* 0xFC04_401D -> 0xFC04_401D - eDMA Clear Error Register */ vubyte ssrt; /* 0xFC04_401E -> 0xFC04_401E - eDMA Set START Bit Register */ vubyte cdne; /* 0xFC04_401F -> 0xFC04_401F - eDMA Clear DONE Status Bit Register */ vudword inth; /* 0xFC04_4020 -> 0xFC04_4023 - eDMA Interrupt Request High Register */ vudword intl; /* 0xFC04_4024 -> 0xFC04_4027 - eDMA Interrupt Request Low Register */ vudword errh; /* 0xFC04_4028 -> 0xFC04_402B - eDMA Error High Register */ vudword errl; /* 0xFC04_402C -> 0xFC04_402F - eDMA Error Low Register */ vudword rsh; /* 0xFC04_4030 -> 0xFC04_4033 - eDMA Hardware Request Status High */ vudword rsl; /* 0xFC04_4034 -> 0xFC04_4037 - eDMA Hardware Request Status Low */ vubyte pack00[200]; /* 0xFC04_4038 -> 0xFC04_40FF - RESERVED */ vubyte dchpri[64]; /* 0xFC04_4100 -> 0xFC04_413F - eDMA Channel 0-64 Priority Registers */ vubyte pack05[3776]; /* 0xFC04_4140 -> 0xFC04_4FFF - RESERVED */ edma_tcdstruct tcd[64]; /* 0xFC04_5000 -> 0xFC04_57FF - Transfer Control Descriptor 0-64 */ } edmastruct; /* * INTERRUPT CONTROLLER 0-2 (intc[3] = 0xFC04_8000 -> 0xFC05_3FFF) */ typedef struct { vudword iprh; /* 0x0000 -> 0x0003 - Interrupt Pending Register High */ vudword iprl; /* 0x0004 -> 0x0007 - Interrupt Pending Register Low */ vudword imrh; /* 0x0008 -> 0x000B - Interrupt Mask Register High */ vudword imrl; /* 0x000C -> 0x000F - Interrupt Mask Register Low */ vudword intfrch; /* 0x0010 -> 0x0013 - Interrupt Force Register High */ vudword intfrcl; /* 0x0014 -> 0x0017 - Interrupt Force Register Low */ vubyte pack00[2]; /* 0x0018 -> 0x0019 - RESERVED */ vuword iconfig; /* 0x001A -> 0x001B - Interrupt Configuration Register */ vubyte simr; /* 0x001C -> 0x001C - Set Interrupt Mask */ vubyte cimr; /* 0x001D -> 0x001D - Clear Interrupt Mask */ vubyte clmask; /* 0x001E -> 0x001E - Current Level Mask */ vubyte slmask; /* 0x001F -> 0x001F - Saved Level Mask */ vubyte pack01[32]; /* 0x0020 -> 0x003F - RESERVED */ vubyte icrn[64]; /* 0x0040 -> 0x007F - Interrupt Control Registers (0-63) */ vubyte pack02[96]; /* 0x0080 -> 0x00DF - RESERVED */ vubyte swackr; /* 0x00E0 -> 0x00E0 - Software IACK Register */ vubyte pack03[3]; /* 0x00E1 -> 0x00E3 - RESERVED */ vubyte l1ackr; /* 0x00E4 -> 0x00E4 - Level 1 IACK Register */ vubyte pack04[3]; /* 0x00E5 -> 0x00E7 - RESERVED */ vubyte l2ackr; /* 0x00E8 -> 0x00E8 - Level 2 IACK Register */ vubyte pack05[3]; /* 0x00E9 -> 0x00EB - RESERVED */ vubyte l3ackr; /* 0x00EC -> 0x00EC - Level 3 IACK Register */ vubyte pack06[3]; /* 0x00ED -> 0x00EF - RESERVED */ vubyte l4ackr; /* 0x00F0 -> 0x00F0 - Level 4 IACK Register */ vubyte pack07[3]; /* 0x00F1 -> 0x00F3 - RESERVED */ vubyte l5ackr; /* 0x00F4 -> 0x00F4 - Level 5 IACK Register */ vubyte pack08[3]; /* 0x00F5 -> 0x00F7 - RESERVED */ vubyte l6ackr; /* 0x00F8 -> 0x00F8 - Level 6 IACK Register */ vubyte pack09[3]; /* 0x00F9 -> 0x00FB - RESERVED */ vubyte l7ackr; /* 0x00FC -> 0x00FC - Level 7 IACK Register */ vubyte pack10[16131]; /* 0x00FD -> 0x3FFF - RESERVED */ } intcstruct; /* * GLOBAL INTERRUPT ACKNOWLEDGE CYCLES */ typedef struct { vubyte gswiack; /* 0xFC05_40E0 -> 0xFC05_40E0 - Global Software Interrupt Acknowledge */ vubyte pack00[3]; /* 0xFC05_40E1 -> 0xFC05_40E3 - RESERVED */ vubyte gl1iack; /* 0xFC05_40E4 -> 0xFC05_40E4 - Global Level 1 Interrupt Acknowledge Register */ vubyte pack01[3]; /* 0xFC05_40E5 -> 0xFC05_40E7 - RESERVED */ vubyte gl2iack; /* 0xFC05_40E8 -> 0xFC05_40E8 - Global Level 2 Interrupt Acknowledge Register */ vubyte pack02[3]; /* 0xFC05_40E9 -> 0xFC05_40EB - RESERVED */ vubyte gl3iack; /* 0xFC05_40EC -> 0xFC05_40EC - Global Level 3 Interrupt Acknowledge Register */ vubyte pack03[3]; /* 0xFC05_40ED -> 0xFC05_40EF - RESERVED */ vubyte gl4iack; /* 0xFC05_40F0 -> 0xFC05_40F0 - Global Level 4 Interrupt Acknowledge Register */ vubyte pack04[3]; /* 0xFC05_40F1 -> 0xFC05_40F3 - RESERVED */ vubyte gl5iack; /* 0xFC05_40F4 -> 0xFC05_40F4 - Global Level 5 Interrupt Acknowledge Register */ vubyte pack05[3]; /* 0xFC05_40F5 -> 0xFC05_40F7 - RESERVED */ vubyte gl6iack; /* 0xFC05_40F8 -> 0xFC05_40F8 - Global Level 6 Interrupt Acknowledge Register */ vubyte pack06[3]; /* 0xFC05_40F9 -> 0xFC05_40FB - RESERVED */ vubyte gl7iack; /* 0xFC05_40FC -> 0xFC05_40FC - Global Level 7 Interrupt Acknowledge Register */ vubyte pack07[3]; /* 0xFC05_40FD -> 0xFC05_40FF - RESERVED */ } intc_iackstruct; /* * I2C MODULE 0 */ //typedef struct { // vubyte i2adr; /* 0xFC05_8000 -> 0xFC05_8000 - I2C Address Register */ // vubyte pack00[3]; /* 0xFC05_8001 -> 0xFC05_8003 - RESERVED */ // vubyte i2fdr; /* 0xFC05_8004 -> 0xFC05_8004 - I2C Frequency Divider Register */ // vubyte pack01[3]; /* 0xFC05_8005 -> 0xFC05_8007 - RESERVED */ // vubyte i2cr; /* 0xFC05_8008 -> 0xFC05_8008 - I2C Control Register */ // vubyte pack02[3]; /* 0xFC05_8009 -> 0xFC05_800B - RESERVED */ // vubyte i2sr; /* 0xFC05_800C -> 0xFC05_800C - I2C Status Register */ // vubyte pack03[3]; /* 0xFC05_800D -> 0xFC05_800F - RESERVED */ // vubyte i2dr; /* 0xFC05_8010 -> 0xFC05_8010 - I2C Data I/O Register */ // vubyte pack04[3]; /* 0xFC05_8011 -> 0xFC05_8013 - RESERVED */ //} i2c0struct; /* * DMA SERIAL PERIPHERAL INTERFACE 0 */ //typedef struct { // vudword mcr; /* 0xFC05_C000 -> 0xFC05_C003 - Module Configuration Register */ // vubyte pack00[4]; /* 0xFC05_C004 -> 0xFC05_C007 - RESERVED */ // vudword tcr; /* 0xFC05_C008 -> 0xFC05_C00B - Transfer Count Register */ // vudword ctar[8]; /* 0xFC05_C00C -> 0xFC05_C02B - Clock and Transfer Attributes Register 0-7 */ // vudword sr; /* 0xFC05_C02C -> 0xFC05_C02F - Status Register */ // vudword rser; /* 0xFC05_C030 -> 0xFC05_C033 - DMA/Interrupt Request Select and Enable Register */ // vudword pushr; /* 0xFC05_C034 -> 0xFC05_C037 - Push Tx FIFO Register */ // vudword popr; /* 0xFC05_C038 -> 0xFC05_C03B - Pop Rx FIFO Register */ // vudword txfr[16]; /* 0xFC05_C03C -> 0xFC05_C07B - Transmit FIFO Register 0-15 */ // vudword rxfr[16]; /* 0xFC05_C07C -> 0xFC05_C0BB - Receive FIFO Register 0-15 */ //} dspi0struct; /* * UART MODULE 0-3 (uarts[4] = 0xFC06_0000 -> 0xFC06_FFFF) */ typedef struct { vubyte umr; /* 0x0000 -> 0x0000 - UART Mode Registers */ vubyte pack00[3]; /* 0x0001 -> 0x0003 - RESERVED */ vubyte usr; /* 0x0004 -> 0x0004 - (Read) UART Status Register (Write) UART Clock Select Register */ vubyte pack01[3]; /* 0x0005 -> 0x0007 - RESERVED */ vubyte ucr; /* 0x0008 -> 0x0008 - (Read) Do Not Access (Write) UART Command Register */ vubyte pack02[3]; /* 0x0009 -> 0x000B - RESERVED */ vubyte utb; /* 0x000C -> 0x000C - (Read) UART Receive Buffer (Write) UART Transmit Buffer */ vubyte pack03[3]; /* 0x000D -> 0x000F - RESERVED */ vubyte uipcr; /* 0x0010 -> 0x0010 - (Read) UART Input Port Change Register (Write) UART Auxiliary Control Register */ vubyte pack04[3]; /* 0x0011 -> 0x0013 - RESERVED */ vubyte uisr; /* 0x0014 -> 0x0014 - (Read) UART Interrupt Status Register (Write) UART Interrupt Mask Register */ vubyte pack05[3]; /* 0x0015 -> 0x0017 - RESERVED */ vubyte dur; /* 0x0018 -> 0x0018 - (Read) Do Not Access (Write) UART Divider Upper Register */ vubyte pack06[3]; /* 0x0019 -> 0x001B - RESERVED */ vubyte dlr; /* 0x001C -> 0x001C - (Read) Do Not Access (Write) UART Divider Lower Register */ vubyte pack07[23]; /* 0x001D -> 0x0033 - RESERVED */ vubyte uip; /* 0x0034 -> 0x0034 - (Read) UART Input Port Register (Write) Do Not Access */ vubyte pack08[3]; /* 0x0035 -> 0x0037 - RESERVED */ vubyte ops; /* 0x0038 -> 0x0038 - (Read) Do Not Access (Write) UART Output Port Bit Set Command Register */ vubyte pack09[3]; /* 0x0039 -> 0x003B - RESERVED */ vubyte opr; /* 0x003C -> 0x003C - (Read) Do Not Access (Write) UART Output Port Bit Reset Command Register */ vubyte pack10[16323]; /* 0x003D -> 0x3FFF - RESERVED */ } uartstruct; /* * DMA TIMER MODULE 0-3 (timer[4] = 0xFC07_0000 -> 0xFC07_FFFF) */ typedef struct { vuword tmr; /* 0x0000 -> 0x0001 - DMA Timer Mode Register */ vubyte txmr; /* 0x0002 -> 0x0002 - DMA Timer Extended Mode Register */ vubyte ter; /* 0x0003 -> 0x0003 - DMA Timer Event Register */ vudword trr; /* 0x0004 -> 0x0007 - DMA Timer Reference Register */ vudword tcr; /* 0x0008 -> 0x000B - DMA Timer Capture Register */ vudword tcn; /* 0x000C -> 0x000F - DMA Timer Counter Register */ vubyte pack00[16368]; /* 0x0010 -> 0x3FFF - RESERVED */ } timerstruct; /* * PROGRAMMABLE INTERRUPT TIMER MODULE 0-3 (pit[4] = 0xFC08_0000 -> 0xFC08_FFFF) */ typedef struct { vuword pcsr; /* 0x0000 -> 0x0001 - PIT Control and Status Register */ vuword pmr; /* 0x0002 -> 0x0003 - PIT Modulus Register */ vuword pcntr; /* 0x0004 -> 0x0005 - PIT Count Register */ vubyte pack00[16378]; /* 0x0006 -> 0x3FFF - RESERVED */ } pitstruct; /* * EDGE PORT MODULE */ typedef struct { vuword eppar; /* 0xFC09_0000 -> 0xFC09_0001 - EPORT Pin Assignment Register */ vubyte epddr; /* 0xFC09_0002 -> 0xFC09_0002 - EPORT Data Direction Register */ vubyte epier; /* 0xFC09_0003 -> 0xFC09_0003 - EPORT Interrupt Enable Register */ vubyte epdr; /* 0xFC09_0004 -> 0xFC09_0004 - EPORT Data Register */ vubyte eppdr; /* 0xFC09_0005 -> 0xFC09_0005 - EPORT Pin Data Register */ vubyte epfr; /* 0xFC09_0006 -> 0xFC09_0006 - EPORT Flag Register */ vubyte pack00; /* 0xFC09_0007 -> 0xFC09_0007 - RESERVED */ } eportstruct; /* * ANALOG-TO-DIGITAL CONVERTER */ typedef struct { vuword cr1; /* 0xFC09_4000 -> 0xFC09_4001 - Control Register 1 */ vuword cr2; /* 0xFC09_4002 -> 0xFC09_4003 - Control Register 2 */ vuword zccr; /* 0xFC09_4004 -> 0xFC09_4005 - Zero Crossing Control Register */ vuword lst1; /* 0xFC09_4006 -> 0xFC09_4007 - Channel List Register 1 */ vuword lst2; /* 0xFC09_4008 -> 0xFC09_4009 - Channel List Register 2 */ vuword sdis; /* 0xFC09_400A -> 0xFC09_400B - Sample Disable Register */ vuword sr; /* 0xFC09_400C -> 0xFC09_400D - Status Register */ vuword lsr; /* 0xFC09_400E -> 0xFC09_400F - Limit Status Register */ vuword zcsr; /* 0xFC09_4010 -> 0xFC09_4011 - Zero Crossing Status Register */ vuword rslt[8]; /* 0xFC09_4012 -> 0xFC09_4021 - Result Register 0-7 */ vuword llmt[8]; /* 0xFC09_4022 -> 0xFC09_4031 - Low Limit Register 0-7 */ vuword hlmt[8]; /* 0xFC09_4032 -> 0xFC09_4041 - High Limit Register 0-7 */ vuword ofs[8]; /* 0xFC09_4042 -> 0xFC09_4051 - Offset Register 0-7 */ vuword pwr; /* 0xFC09_4052 -> 0xFC09_4053 - Power Control Register */ vuword cal; /* 0xFC09_4054 -> 0xFC09_4055 - Calibration Register */ vuword pwr2; /* 0xFC09_4056 -> 0xFC09_4057 - Power Control Register 2 */ vuword div; /* 0xFC09_4058 -> 0xFC09_4059 - Conversion Divisor Register */ vuword asdiv; /* 0xFC09_405A -> 0xFC09_405B - Auto-Standby Divisor Register */ } adcstruct; /* * DIGITAL-TO-ANALOG CONVERTER 0-1 (dac[2] = 0xFC09_8000 -> 0xFC09_FFFF) */ typedef struct { vuword cr; /* 0x0000 -> 0x0001 - Control Register */ vuword data; /* 0x0002 -> 0x0003 - Buffered Data Register */ vuword step; /* 0x0004 -> 0x0005 - Step Size Register */ vuword min; /* 0x0006 -> 0x0007 - Minimum Value Register */ vuword max; /* 0x0008 -> 0x0009 - Maximum Value Register */ vuword sr; /* 0x000A -> 0x000B - Status Register */ vuword filtcnt; /* 0x000C -> 0x000D - Filter Count Register */ vubyte pack00[16370]; /* 0x000E -> 0x3FFF - RESERVED */ } dacstruct; /* * SERIAL BOOT FACILITY (SBF) */ typedef struct { vuword sbfsr; /* 0xFC0A_0020 -> 0xFC0A_0021 - Serial Boot Facility Status Register */ vuword sbfcr; /* 0xFC0A_0022 -> 0xFC0A_0023 - Serial Boot Facility Control Register */ } sbfstruct; /* * REAL-TIME CLOCK */ typedef struct { vuword yearmon; /* 0xFC0A_8000 -> 0xFC0A_8001 - Month and Year Counter Register */ vuword days; /* 0xFC0A_8002 -> 0xFC0A_8003 - Day and Day-of-Week Counter Register */ vuword hourmin; /* 0xFC0A_8004 -> 0xFC0A_8005 - Hour and Minute Counter Register */ vuword seconds; /* 0xFC0A_8006 -> 0xFC0A_8007 - Second Counter Register */ vuword alm_yrmon; /* 0xFC0A_8008 -> 0xFC0A_8009 - Year and Month Alarm Register */ vuword alm_days; /* 0xFC0A_800A -> 0xFC0A_800B - Day Alarm Register */ vuword alm_hm; /* 0xFC0A_800C -> 0xFC0A_800D - Hour and Minute Alarm Register */ vuword alm_sec; /* 0xFC0A_800E -> 0xFC0A_800F - Second Alarm Register */ vuword cr; /* 0xFC0A_8010 -> 0xFC0A_8011 - Control Register */ vuword sr; /* 0xFC0A_8012 -> 0xFC0A_8013 - Status Register */ vuword isr; /* 0xFC0A_8014 -> 0xFC0A_8015 - Interrupt Status Register */ vuword ier; /* 0xFC0A_8016 -> 0xFC0A_8017 - Interrupt Enable Register */ vuword count_dn; /* 0xFC0A_8018 -> 0xFC0A_8019 - Countdown Timer Register */ vubyte pack00[6]; /* 0xFC0A_801A -> 0xFC0A_8019 - RESERVED */ vuword cfg; /* 0xFC0A_8020 -> 0xFC0A_8021 - RTC config register */ vuword dst_hour; /* 0xFC0A_8022 -> 0xFC0A_8023 - Daylight Saving Time Hour Register */ vuword dst_mon; /* 0xFC0A_8024 -> 0xFC0A_8025 - Daylight Saving Time Month Register */ vuword dst_day; /* 0xFC0A_8026 -> 0xFC0A_8027 - Daylight Saving Time Day Register */ vuword compen; /* 0xFC0A_8028 -> 0xFC0A_8029 - Compensation Register */ vubyte pack01[8]; /* 0xFC0A_802A -> 0xFC0A_8031 - RESERVED */ vuword cntrh; /* 0xFC0A_8032 -> 0xFC0A_8033 - Count Up High Register */ vuword cntrl; /* 0xFC0A_8034 -> 0xFC0A_8035 - Count Up Low Register */ vubyte pack02[10]; /* 0xFC0A_8036 -> 0xFC0A_803F - RESERVED */ vudword stdbyram[512]; /* 0xFC0A_8040 -> 0xFC0A_883F - Standby RAM */ } rtcstruct; /* * SUBSCRIBER IDENTIFICATION MODULE */ typedef struct { vudword cr1; /* 0xFC0A_C000 -> 0xFC0A_C003 - SIM Port 1 Control Register */ vudword setup; /* 0xFC0A_C004 -> 0xFC0A_C007 - SIM Setup Register */ vudword detect1; /* 0xFC0A_C008 -> 0xFC0A_C00B - SIM Port 1 Detect Register */ vudword tbuf1; /* 0xFC0A_C00C -> 0xFC0A_C00F - SIM Port 1 Transmit Buffer Register */ vudword rbuf1; /* 0xFC0A_C010 -> 0xFC0A_C013 - SIM Port 1 Receive Buffer Register */ vudword cr0; /* 0xFC0A_C014 -> 0xFC0A_C017 - SIM Port 0 Control Register */ vudword cr; /* 0xFC0A_C018 -> 0xFC0A_C01B - SIM Control Register */ vudword pre; /* 0xFC0A_C01C -> 0xFC0A_C01F - SIM Clock Prescaler Register */ vudword rthr; /* 0xFC0A_C020 -> 0xFC0A_C023 - SIM Receive Threshold Register */ vudword en; /* 0xFC0A_C024 -> 0xFC0A_C027 - SIM Enable Register */ vudword tsr; /* 0xFC0A_C028 -> 0xFC0A_C02B - SIM Transmit Status Register */ vudword rsr; /* 0xFC0A_C02C -> 0xFC0A_C02F - SIM Receive Status Register */ vudword imr; /* 0xFC0A_C030 -> 0xFC0A_C033 - SIM Interrupt Mask Register */ vudword tbuf0; /* 0xFC0A_C034 -> 0xFC0A_C037 - SIM Port 0 Transmit Buffer Register */ vudword rbuf0; /* 0xFC0A_C038 -> 0xFC0A_C03B - SIM Port 0 Receive Buffer Reigster */ vudword detect0; /* 0xFC0A_C03C -> 0xFC0A_C03F - SIM Port 0 Detect Register */ vudword format0; /* 0xFC0A_C040 -> 0xFC0A_C043 - SIM Data Format Register */ vudword tthr; /* 0xFC0A_C044 -> 0xFC0A_C047 - SIM Transmit Threshold Register */ vudword tgcr; /* 0xFC0A_C048 -> 0xFC0A_C04B - SIM Transmit Guard Control Register */ vudword odcr; /* 0xFC0A_C04C -> 0xFC0A_C04F - SIM Open Drain Configuration Control Register */ vudword rcr; /* 0xFC0A_C050 -> 0xFC0A_C053 - SIM Reset Control Register */ vudword cwtr; /* 0xFC0A_C054 -> 0xFC0A_C057 - SIM Character Wait Time Register */ vudword gpcnt; /* 0xFC0A_C058 -> 0xFC0A_C05B - SIM General Purpose Counter Register */ vudword div; /* 0xFC0A_C05C -> 0xFC0A_C05F - SIM Divisor Register */ vudword bwt; /* 0xFC0A_C060 -> 0xFC0A_C063 - SIM Block Wait Time Register */ vudword bgt; /* 0xFC0A_C064 -> 0xFC0A_C067 - SIM Block Guard Time Register */ vudword bwth; /* 0xFC0A_C068 -> 0xFC0A_C06B - SIM Block Wait Time Register High */ vudword tfsr; /* 0xFC0A_C06C -> 0xFC0A_C06F - SIM Transmit FIFO Status Register */ vudword rfcr; /* 0xFC0A_C070 -> 0xFC0A_C073 - SIM Receive FIFO Counter Register */ vudword rfwp; /* 0xFC0A_C074 -> 0xFC0A_C077 - SIM Receive FIFO Write Pointer Register */ vudword rfrp; /* 0xFC0A_C078 -> 0xFC0A_C07B - SIM Receive FIFO Read Pointer Register */ } simstruct; /* * USB ON-THE-GO */ typedef struct { vudword id; /* 0xFC0B_0000 -> 0xFC0B_0003 - Identification Register */ vudword hwgeneral; /* 0xFC0B_0004 -> 0xFC0B_0007 - General Hardware Parameters */ vudword hwhost; /* 0xFC0B_0008 -> 0xFC0B_000B - Host Hardware Parameters */ vudword hwdevice; /* 0xFC0B_000C -> 0xFC0B_000F - Device Hardware Parameters */ vudword hwtxbuf; /* 0xFC0B_0010 -> 0xFC0B_0013 - Tx Buffer Hardware Parameters */ vudword hwrxbuf; /* 0xFC0B_0014 -> 0xFC0B_0017 - Rx Buffer Hardware Parameters */ vubyte pack00[104]; /* 0xFC0B_0018 -> 0xFC0B_007F - RESERVED */ vudword gptimer0ld; /* 0xFC0B_0080 -> 0xFC0B_0083 - General Purpose Timer 0 Load */ vudword gptimer0ctl; /* 0xFC0B_0084 -> 0xFC0B_0087 - General Purpose Timer 0 Control */ vudword gptimer1ld; /* 0xFC0B_0088 -> 0xFC0B_008B - General Purpose Timer 1 Load */ vudword gptimer1ctl; /* 0xFC0B_008C -> 0xFC0B_008F - General Purpose Timer 1 Control */ vubyte pack01[112]; /* 0xFC0B_0090 -> 0xFC0B_00FF - RESERVED */ vuword hciversion; /* 0xFC0B_0100 -> 0xFC0B_0101 - Host Interface Version Number */ vubyte pack02; /* 0xFC0B_0102 -> 0xFC0B_0102 - RESERVED */ vubyte caplength; /* 0xFC0B_0103 -> 0xFC0B_0103 - Capability Register Length */ vudword hcsparams; /* 0xFC0B_0104 -> 0xFC0B_0107 - Host Structural Parameters */ vudword hccparams; /* 0xFC0B_0108 -> 0xFC0B_010B - Host Capability Parameters */ vubyte pack03[22]; /* 0xFC0B_010C -> 0xFC0B_0121 - RESERVED */ vuword dciversion; /* 0xFC0B_0122 -> 0xFC0B_0123 - Device Interface Version Number */ vudword dccparams; /* 0xFC0B_0124 -> 0xFC0B_0127 - Device Capability Parameters */ vubyte pack04[24]; /* 0xFC0B_0128 -> 0xFC0B_013F - RESERVED */ vudword usbcmd; /* 0xFC0B_0140 -> 0xFC0B_0143 - USB Command */ vudword usbsts; /* 0xFC0B_0144 -> 0xFC0B_0147 - USB Status */ vudword usbintr; /* 0xFC0B_0148 -> 0xFC0B_014B - USB Interrupt Enable */ vudword frindex; /* 0xFC0B_014C -> 0xFC0B_014F - USB Frame Index */ vubyte pack05[4]; /* 0xFC0B_0150 -> 0xFC0B_0153 - RESERVED */ vudword periodiclstbase; /* 0xFC0B_0154 -> 0xFC0B_0157 - (Host Mode) Periodic Frame List Base Address - (Device Mode) Device Address */ vudword asynclistaddr; /* 0xFC0B_0158 -> 0xFC0B_015B - (Host Mode) Current Asynchronous List Address - (Device Mode) Address at Endpoint List */ vudword ttctrl; /* 0xFC0B_015C -> 0xFC0B_015F - Host TT Asynchronous Buffer Control */ vudword burstsize; /* 0xFC0B_0160 -> 0xFC0B_0163 - Master Interface Data Burst Size */ vudword txfilltuning; /* 0xFC0B_0164 -> 0xFC0B_0167 - Host Transmit FIFO Tuning Control */ vubyte pack06[8]; /* 0xFC0B_0168 -> 0xFC0B_016F - RESERVED */ vudword ulpi_viewport; /* 0xFC0B_0170 -> 0xFC0B_0173 - ULPI Register Access */ vubyte pack07[12]; /* 0xFC0B_0174 -> 0xFC0B_017F - RESERVED */ vudword configflag; /* 0xFC0B_0180 -> 0xFC0B_0183 - Configure Flag Register */ vudword portsc1; /* 0xFC0B_0184 -> 0xFC0B_0187 - Port Status/Control */ vubyte pack08[28]; /* 0xFC0B_0188 -> 0xFC0B_01A3 - RESERVED */ vudword otgsc; /* 0xFC0B_01A4 -> 0xFC0B_01A7 - On-the-Go Status and Control */ vudword mode; /* 0xFC0B_01A8 -> 0xFC0B_01AB - USB Mode Register */ vudword epsetupsr; /* 0xFC0B_01AC -> 0xFC0B_01AF - Endpoint Setup Status Register */ vudword epprime; /* 0xFC0B_01B0 -> 0xFC0B_01B3 - Endpoint Initialization */ vudword epflush; /* 0xFC0B_01B4 -> 0xFC0B_01B7 - Endpoint De-initialize */ vudword epsr; /* 0xFC0B_01B8 -> 0xFC0B_01BB - Endpoint Status Register */ vudword epcomplete; /* 0xFC0B_01BC -> 0xFC0B_01BF - Endpoint Complete */ vudword epcr0; /* 0xFC0B_01C0 -> 0xFC0B_01C3 - Endpoint Control Register 0 */ vudword epcr1; /* 0xFC0B_01C4 -> 0xFC0B_01C7 - Endpoint Control Register 1 */ vudword epcr2; /* 0xFC0B_01C8 -> 0xFC0B_01CB - Endpoint Control Register 2 */ vudword epcr3; /* 0xFC0B_01CC -> 0xFC0B_01CF - Endpoint Control Register 3 */ } usb_otgstruct; /* * USB HOST CONTROLLER */ typedef struct { vudword id; /* 0xFC0B_4000 -> 0xFC0B_4003 - Identification Register */ vudword hwgeneral; /* 0xFC0B_4004 -> 0xFC0B_4007 - General Hardware Parameters */ vudword hwhost; /* 0xFC0B_4008 -> 0xFC0B_400B - Host Hardware Parameters */ vubyte pack00[4]; /* 0xFC0B_400C -> 0xFC0B_400F - RESERVED */ vudword hwtxbuf; /* 0xFC0B_4010 -> 0xFC0B_4013 - Tx Buffer Hardware Parameters */ vudword hwrxbuf; /* 0xFC0B_4014 -> 0xFC0B_4017 - Rx Buffer Hardware Parameters */ vubyte pack01[232]; /* 0xFC0B_4018 -> 0xFC0B_40FF - RESERVED */ vuword hciversion; /* 0xFC0B_4100 -> 0xFC0B_4101 - Host Interface Version Number */ vubyte pack02; /* 0xFC0B_4102 -> 0xFC0B_4102 - RESERVED */ vubyte caplength; /* 0xFC0B_4103 -> 0xFC0B_4103 - Capability Register Length */ vudword hcsparams; /* 0xFC0B_4104 -> 0xFC0B_4107 - Host Structural Parameters */ vudword hccparams; /* 0xFC0B_4108 -> 0xFC0B_410B - Host Capability Parameters */ vubyte pack03[52]; /* 0xFC0B_410C -> 0xFC0B_413F - RESERVED */ vudword usbcmd; /* 0xFC0B_4140 -> 0xFC0B_4143 - USB Command */ vudword usbsts; /* 0xFC0B_4144 -> 0xFC0B_4147 - USB Status */ vudword usbintr; /* 0xFC0B_4148 -> 0xFC0B_414B - USB Interrupt Enable */ vudword frindex; /* 0xFC0B_414C -> 0xFC0B_414F - USB Frame Index */ vubyte pack04[4]; /* 0xFC0B_4150 -> 0xFC0B_4153 - RESERVED */ vudword periodiclstbase; /* 0xFC0B_4154 -> 0xFC0B_4157 - Periodic Frame List Base Address */ vudword asynclistaddr; /* 0xFC0B_4158 -> 0xFC0B_415B - Current Asynchronous List Address */ vudword ttctrl; /* 0xFC0B_415C -> 0xFC0B_415F - Host TT Asynchronous Buffer Control */ vudword burstsize; /* 0xFC0B_4160 -> 0xFC0B_4163 - Master Interface Data Burst Size */ vudword txfilltuning; /* 0xFC0B_4164 -> 0xFC0B_4167 - Host Transmit FIFO Tuning Control */ vubyte pack05[24]; /* 0xFC0B_4168 -> 0xFC0B_417F - RESERVED */ vudword configflag; /* 0xFC0B_4180 -> 0xFC0B_4183 - Configure Flag Register */ vudword portsc1; /* 0xFC0B_4184 -> 0xFC0B_4187 - Port Status/Control */ vubyte pack06[32]; /* 0xFC0B_4188 -> 0xFC0B_41A7 - RESERVED */ vudword mode; /* 0xFC0B_41A8 -> 0xFC0B_41AB - USB Mode Register */ } usb_hoststruct; /* * DDR1/2 SDRAM MEMORY CONTROLLER */ typedef struct { vudword cr[64]; /* 0xFC0B_8000 -> 0xFC0B_80FF - Control Register 0-63 (46-52, 54, 61-63 reserved) */ vubyte pack00[172]; /* 0xFC0B_8100 -> 0xFC0B_81AB - RESERVED */ vudword padcr; /* 0xFC0B_81AC -> 0xFC0B_81AF - I/O Pad Control Register */ } ddrmcstruct; /* * SYNCHRONOUS SERIAL INTERFACE 0 */ typedef struct { vudword tx0; /* 0xFC0B_C000 -> 0xFC0B_C003 - Transmit Data Register 0 */ vudword tx1; /* 0xFC0B_C004 -> 0xFC0B_C007 - Transmit Data Register 1 */ vudword rx0; /* 0xFC0B_C008 -> 0xFC0B_C00B - Receive Data Register 0 */ vudword rx1; /* 0xFC0B_C00C -> 0xFC0B_C00F - Receive Data Register 1 */ vudword cr; /* 0xFC0B_C010 -> 0xFC0B_C013 - Control Register */ vudword isr; /* 0xFC0B_C014 -> 0xFC0B_C017 - Interrupt Status Register */ vudword ier; /* 0xFC0B_C018 -> 0xFC0B_C01B - Interrupt Enable Register */ vudword tcr; /* 0xFC0B_C01C -> 0xFC0B_C01F - Transmit Configuration Register */ vudword rcr; /* 0xFC0B_C020 -> 0xFC0B_C023 - Receive Configuration Register */ vudword ccr; /* 0xFC0B_C024 -> 0xFC0B_C027 - Clock Control Register */ vubyte pack00[4]; /* 0xFC0B_C028 -> 0xFC0B_C02B - RESERVED */ vudword fcsr; /* 0xFC0B_C02C -> 0xFC0B_C02F - FIFO Control/Status Register */ vubyte pack01[8]; /* 0xFC0B_C030 -> 0xFC0B_C037 - RESERVED */ vudword acr; /* 0xFC0B_C038 -> 0xFC0B_C03B - AC97 Control Register */ vudword acadd; /* 0xFC0B_C03C -> 0xFC0B_C03F - AC97 Command Address Register */ vudword acdat; /* 0xFC0B_C040 -> 0xFC0B_C043 - AC97 Command Data Register */ vudword atag; /* 0xFC0B_C044 -> 0xFC0B_C047 - AC97 Tag Register */ vudword tmask; /* 0xFC0B_C048 -> 0xFC0B_C04B - Transmit Time Slot Mask Register */ vudword rmask; /* 0xFC0B_C04C -> 0xFC0B_C04F - Receive Time Slot Mask Register */ vudword accsr; /* 0xFC0B_C050 -> 0xFC0B_C053 - AC97 Channel Status Register */ vudword accen; /* 0xFC0B_C054 -> 0xFC0B_C057 - AC97 Channel Enable Register */ vudword accdis; /* 0xFC0B_C058 -> 0xFC0B_C05B - AC97 Channel Disable Register */ } ssi0struct; /* * CLOCK MODULE (PHASE-LOCKED LOOP) */ typedef struct { vudword pll_cr; /* 0xFC0C_0000 -> 0xFC0C_0003 - PLL Control Register */ vudword pll_dr; /* 0xFC0C_0004 -> 0xFC0C_0007 - PLL Divider Register */ vudword pll_sr; /* 0xFC0C_0008 -> 0xFC0C_000B - PLL Status Register */ } clockstruct; /* * RANDOM NUMBER GENERATOR */ typedef struct { vudword ver; /* 0xFC0C_4000 -> 0xFC0C_4003 - Version ID Register */ vudword cmd; /* 0xFC0C_4004 -> 0xFC0C_4007 - Command Register */ vudword cr; /* 0xFC0C_4008 -> 0xFC0C_400B - Control Register */ vudword sr; /* 0xFC0C_400C -> 0xFC0C_400F - Status Register */ vudword esr; /* 0xFC0C_4010 -> 0xFC0C_4013 - Error Status Register */ vudword out; /* 0xFC0C_4014 -> 0xFC0C_4017 - Output FIFO */ vudword er; /* 0xFC0C_4018 -> 0xFC0C_401B - Entropy Register */ } rngstruct; /* * SYNCHRONOUS SERIAL INTERFACE 1 */ typedef struct { vudword tx0; /* 0xFC0C_8000 -> 0xFC0C_8003 - Transmit Data Register 0 */ vudword tx1; /* 0xFC0C_8004 -> 0xFC0C_8007 - Transmit Data Register 1 */ vudword rx0; /* 0xFC0C_8008 -> 0xFC0C_800B - Receive Data Register 0 */ vudword rx1; /* 0xFC0C_800C -> 0xFC0C_800F - Receive Data Register 1 */ vudword cr; /* 0xFC0C_8010 -> 0xFC0C_8013 - Control Register */ vudword isr; /* 0xFC0C_8014 -> 0xFC0C_8017 - Interrupt Status Register */ vudword ier; /* 0xFC0C_8018 -> 0xFC0C_801B - Interrupt Enable Register */ vudword tcr; /* 0xFC0C_801C -> 0xFC0C_801F - Transmit Configuration Register */ vudword rcr; /* 0xFC0C_8020 -> 0xFC0C_8023 - Receive Configuration Register */ vudword ccr; /* 0xFC0C_8024 -> 0xFC0C_8027 - Clock Control Register */ vubyte pack00[4]; /* 0xFC0C_8028 -> 0xFC0C_802B - RESERVED */ vudword fcsr; /* 0xFC0C_802C -> 0xFC0C_802F - FIFO Control/Status Register */ vubyte pack01[8]; /* 0xFC0C_8030 -> 0xFC0C_8037 - RESERVED */ vudword acr; /* 0xFC0C_8038 -> 0xFC0C_803B - AC97 Control Register */ vudword acadd; /* 0xFC0C_803C -> 0xFC0C_803F - AC97 Command Address Register */ vudword acdat; /* 0xFC0C_8040 -> 0xFC0C_8043 - AC97 Command Data Register */ vudword atag; /* 0xFC0C_8044 -> 0xFC0C_8047 - AC97 Tag Register */ vudword tmask; /* 0xFC0C_8048 -> 0xFC0C_804B - Transmit Time Slot Mask Register */ vudword rmask; /* 0xFC0C_804C -> 0xFC0C_804F - Receive Time Slot Mask Register */ vudword accsr; /* 0xFC0C_8050 -> 0xFC0C_8053 - AC97 Channel Status Register */ vudword accen; /* 0xFC0C_8054 -> 0xFC0C_8057 - AC97 Channel Enable Register */ vudword accdis; /* 0xFC0C_8058 -> 0xFC0C_805B - AC97 Channel Disable Register */ } ssi1struct; /* * ENHANCED SECURE DIGITAL HOST CONTROLLER */ typedef struct { vudword dsaddr; /* 0xFC0C_C000 -> 0xFC0C_C003 - DMA System Address */ vudword blkattr; /* 0xFC0C_C004 -> 0xFC0C_C007 - Block Attributes */ vudword cmdarg; /* 0xFC0C_C008 -> 0xFC0C_C00B - Command Argument */ vudword xfertyp; /* 0xFC0C_C00C -> 0xFC0C_C00F - Command Transfer Type */ vudword cmdrsp0; /* 0xFC0C_C010 -> 0xFC0C_C013 - Command Response 0 */ vudword cmdrsp1; /* 0xFC0C_C014 -> 0xFC0C_C017 - Command Response 1 */ vudword cmdrsp2; /* 0xFC0C_C018 -> 0xFC0C_C01B - Command Response 2 */ vudword cmdrsp3; /* 0xFC0C_C01C -> 0xFC0C_C01F - Command Response 3 */ vudword datport; /* 0xFC0C_C020 -> 0xFC0C_C023 - Data Buffer Access Port */ vudword prsstat; /* 0xFC0C_C024 -> 0xFC0C_C027 - Present State */ vudword proctl; /* 0xFC0C_C028 -> 0xFC0C_C02B - Protocol Control */ vudword sysctl; /* 0xFC0C_C02C -> 0xFC0C_C02F - System Control */ vudword irqstat; /* 0xFC0C_C030 -> 0xFC0C_C033 - Interrupt Status */ vudword irqstaten; /* 0xFC0C_C034 -> 0xFC0C_C037 - Interrupt Status Enable */ vudword irqsigen; /* 0xFC0C_C038 -> 0xFC0C_C03B - Interrupt Signal Enable */ vudword autoc12err; /* 0xFC0C_C03C -> 0xFC0C_C03F - Auto CMD12 Status */ vudword hostcapblt; /* 0xFC0C_C040 -> 0xFC0C_C043 - Host Controller Capabilities */ vudword wml; /* 0xFC0C_C044 -> 0xFC0C_C047 - Watermark Level */ vubyte pack00[8]; /* 0xFC0C_C048 -> 0xFC0C_C04F - RESERVERED */ vudword fevt; /* 0xFC0C_C050 -> 0xFC0C_C053 - Force Event */ vudword admaesr; /* 0xFC0C_C054 -> 0xFC0C_C057 - ADMA Error Status */ vudword admasar; /* 0xFC0C_C058 -> 0xFC0C_C05B - ADMA System Address */ vubyte pack01[160]; /* 0xFC0C_C05C -> 0xFC0C_C0FB - RESERVED */ vudword hostver; /* 0xFC0C_C0FC -> 0xFC0C_C0FF - Host Controller Version */ } sdhcstruct; /* * MIB COUNTER BLOCK RMON TRANSMIT */ typedef struct { vudword drop; /* 0x00 -> 0x03 - Count of Frames Not Counted Correctly (Not Implemented) */ vudword packets; /* 0x04 -> 0x07 - RMON Tx Packet Count */ vudword bc_pkt; /* 0x08 -> 0x0B - RMON Tx Broadcast Packets */ vudword mc_pkt; /* 0x0C -> 0x0F - RMON Tx Multicast Packets */ vudword crc_align; /* 0x10 -> 0x13 - RMON Tx Packets with CRC/Align Error */ vudword undersize; /* 0x14 -> 0x17 - RMON Tx Packets < 64 Bytes, Good CRC */ vudword oversize; /* 0x18 -> 0x1B - RMON Tx Packets > MAX_FL Bytes, Good CRC */ vudword frag; /* 0x1C -> 0x1F - RMON Tx Packets < 64 Bytes, Bad CRC */ vudword jab; /* 0x20 -> 0x23 - RMON Tx Packets > MAX_FL Bytes, Bad CRC */ vudword col; /* 0x24 -> 0x27 - RMON Tx Collision Count */ vudword p64; /* 0x28 -> 0x2B - RMON Tx 64 Byte Packets */ vudword p65to127; /* 0x2C -> 0x2F - RMON Tx 65 to 127 Byte Packets */ vudword p128to255; /* 0x30 -> 0x33 - RMON Tx 128 to 255 Byte Packets */ vudword p256to511; /* 0x34 -> 0x37 - RMON Tx 256 to 511 Byte Packets */ vudword p512to1023; /* 0x38 -> 0x3B - RMON Tx 512 to 1023 Byte Packets */ vudword p1024to2047; /* 0x3C -> 0x3F - RMON Tx 1024 to 2047 Byte Packets */ vudword p_gte2048; /* 0x40 -> 0x43 - RMON Tx Packets with > 2048 Bytes */ vudword octets; /* 0x44 -> 0x47 - RMON Tx Octets */ } rmon_tstruct; /* * MIB COUNTER BLOCK IEEE TRANSMIT */ typedef struct { vudword drop; /* 0x00 -> 0x03 - Count of Frames Not Counted Correctly (Not Implemented) */ vudword frame_ok; /* 0x04 -> 0x07 - Frames Transmitted OK */ vudword scol; /* 0x08 -> 0x0B - Frames Transmitted with Single Collision */ vudword mcol; /* 0x0C -> 0x0F - Frames Transmitted with Multiple Collisions */ vudword def; /* 0x10 -> 0x13 - Frames Transmitted after Deferral Delay */ vudword lcol; /* 0x14 -> 0x17 - Frames Transmitted with Late Collision */ vudword excol; /* 0x18 -> 0x1B - Frames Transmitted with Excessive Collisions */ vudword macerr; /* 0x1C -> 0x1F - Frames Transmitted with Tx FIFO Underrun */ vudword cserr; /* 0x20 -> 0x23 - Frames Transmitted with Carrier Sense Error */ vudword sqe; /* 0x24 -> 0x27 - Frames Transmitted with SQE Error (Not Implemented) */ vudword fdxfc; /* 0x28 -> 0x2B - Flow Control Pause Frames Transmitted */ vudword octets_ok; /* 0x2C -> 0x2F - Octet Count for Frames Transmitted without Error */ } ieee_tstruct; /* * MIB COUNTER BLOCK RMON RECEIVE */ typedef struct { vubyte pack00[4]; /* 0x00 -> 0x03 - RESERVED */ vudword packets; /* 0x04 -> 0x07 - RMON Rx Packet Count */ vudword bc_pkt; /* 0x08 -> 0x0B - RMON Rx Broadcast Packets */ vudword mc_pkt; /* 0x0C -> 0x0F - RMON Rx Multicast Packets */ vudword crc_align; /* 0x10 -> 0x13 - RMON Rx Packets with CRC/Align Error */ vudword undersize; /* 0x14 -> 0x17 - RMON Rx Packets < 64 Bytes, Good CRC */ vudword oversize; /* 0x18 -> 0x1B - RMON Rx > MAX_FL Bytes, Good CRC */ vudword frag; /* 0x1C -> 0x1F - RMON Rx packets < 64 Bytes, Bad CRC */ vudword jab; /* 0x20 -> 0x23 - RMON Rx Packets > MAX_FL Bytes, Bad CRC */ vudword resvd_0; /* 0x24 -> 0x27 - RESERVED */ vudword p64; /* 0x28 -> 0x2B - RMON Rx 64 Byte Packets */ vudword p65to127; /* 0x2C -> 0x2F - RMON Rx 65 to 127 Byte Packets */ vudword p128to255; /* 0x30 -> 0x33 - RMON Rx 128 to 255 Byte Packets */ vudword p256to511; /* 0x34 -> 0x37 - RMON Rx 256 to 511 Byte Packets */ vudword p512to1023; /* 0x38 -> 0x3B - RMON Rx 512 to 1023 Byte Packets */ vudword p1024to2047; /* 0x3C -> 0x3F - RMON Rx 1024 to 2047 Byte Packets */ vudword p_gte2048; /* 0x40 -> 0x43 - RMON Rx Packets with > 2048 Bytes */ vudword octets; /* 0x44 -> 0x47 - RMON Rx Octets */ } rmon_rstruct; /* * MIB COUNTER BLOCK IEEE RECEIVE */ typedef struct { vudword drop; /* 0x00 -> 0x03 - Count of Frames Not Counted Correctly */ vudword frame_ok; /* 0x04 -> 0x07 - Frames Received OK */ vudword crc; /* 0x08 -> 0x0B - Frames Received with CRC Error */ vudword align; /* 0x0C -> 0x0F - Frames Received with Alignment Error */ vudword macerr; /* 0x10 -> 0x13 - Receive FIFO Overflow Count */ vudword fdxfc; /* 0x14 -> 0x17 - Flow Control Pause Frames Received */ vudword octets_ok; /* 0x18 -> 0x1B - Octet Count for Frames Received without Error */ } ieee_rstruct; /* * 10/100 MBPS ETHERNET MAC-NET CORE 0-1 (fec[2] = 0xFC0D_4000 -> 0xFC0D_BFFF) */ typedef struct { vubyte pack00[4]; /* 0x4000 -> 0x4003 - RESERVED */ vudword eir; /* 0x4004 -> 0x4007 - Interrupt Event Register */ vudword eimr; /* 0x4008 -> 0x400B - Interrupt Mask Register */ vubyte pack01[4]; /* 0x400C -> 0x400F - RESERVED */ vudword rdar; /* 0x4010 -> 0x4013 - Receive Descriptor Active Register */ vudword tdar; /* 0x4014 -> 0x4017 - Transmit Descriptor Active Register */ vubyte pack02[12]; /* 0x4018 -> 0x4023 - RESERVED */ vudword ecr; /* 0x4024 -> 0x4027 - Ethernet Control Register */ vubyte pack03[24]; /* 0x4028 -> 0x403F - RESERVED */ vudword mdata; /* 0x4040 -> 0x4043 - MII Data Register (MII Management Frame Register) */ vudword mscr; /* 0x4044 -> 0x4047 - MII Speed Control Register */ vubyte pack04[28]; /* 0x4048 -> 0x4063 - RESERVED */ vudword mibc; /* 0x4064 -> 0x4067 - MIB Control/Status Register */ vubyte pack05[28]; /* 0x4068 -> 0x4083 - RESERVED */ vudword rcr; /* 0x4084 -> 0x4087 - Receive Control Register */ vubyte pack06[60]; /* 0x4088 -> 0x40C3 - RESERVED */ vudword tcr; /* 0x40C4 -> 0x40C7 - Transmit Control Register */ vubyte pack07[28]; /* 0x40C8 -> 0x40E3 - RESERVED */ vudword palr; /* 0x40E4 -> 0x40E7 - Physical Address Low Register */ vudword paur; /* 0x40E8 -> 0x40EB - Physical Address High Register */ vudword opd; /* 0x40EC -> 0x40EF - Opcode/Pause Duration Register */ vubyte pack08[40]; /* 0x40F0 -> 0x4117 - RESERVED */ vudword iaur; /* 0x4118 -> 0x411B - Descriptor Individual Upper Address Register */ vudword ialr; /* 0x411C -> 0x411F - Descriptor Individual Lower Address Register */ vudword gaur; /* 0x4120 -> 0x4123 - Descriptor Group Upper Address Register */ vudword galr; /* 0x4124 -> 0x4127 - Descriptor Group Lower Address Register */ vubyte pack09[28]; /* 0x4128 -> 0x4143 - RESERVED */ vudword tfwr; /* 0x4144 -> 0x4147 - Transmit FIFO Watermark and Store/Foward Control */ vubyte pack10[4]; /* 0x4148 -> 0x414B - RESERVED */ vudword frbr; /* 0x414C -> 0x414F - FIFO Receive Bound Register (Not Implemented) */ vudword frsr; /* 0x4150 -> 0x4153 - FIFO Receive Start Register (Not Implemented) */ vubyte pack11[44]; /* 0x4154 -> 0x417F - RESERVED */ vudword erdsr; /* 0x4180 -> 0x4183 - Receive Descriptor Ring Start Register */ vudword etdsr; /* 0x4184 -> 0x4187 - Transmit Descriptor Ring Start Register */ vudword emrbr; /* 0x4188 -> 0x418B - Maximum Receive Buffer Size */ vubyte pack12[4]; /* 0x418C -> 0x418F - RESERVED */ vudword rsfl; /* 0x4190 -> 0x4193 - Receive FIFO Section Full Threshold */ vudword rsem; /* 0x4194 -> 0x4197 - Receive FIFO Section Empty Threshold */ vudword raem; /* 0x4198 -> 0x419B - Receive FIFO Almost Empty Threshold */ vudword rafl; /* 0x419C -> 0x419F - Receive FIFO Almost Full Threshold */ vudword tsem; /* 0x41A0 -> 0x41A3 - Transmit FIFO Section Empty Threshold */ vudword taem; /* 0x41A4 -> 0x41A7 - Transmit FIFO Almost Empty Threshold */ vudword tafl; /* 0x41A8 -> 0x41AB - Transmit FIFO Almost Full Threshold */ vudword tipg; /* 0x41AC -> 0x41AF - Transmit Inter-Packet Gap */ vudword ftrl; /* 0x41B0 -> 0x41B3 - Frame Truncation Length */ vubyte pack13[12]; /* 0x41B4 -> 0x41BF - RESERVED */ vudword tacc; /* 0x41C0 -> 0x41C3 - Transmit Accelerator Function Configuration */ vudword racc; /* 0x41C4 -> 0x41C7 - Receive Accelerator Function Configuration */ vubyte pack14[56]; /* 0x41C8 -> 0x41FF - RESERVED */ rmon_tstruct fec_rmon_t; /* 0x4200 -> 0x4247 - MIB Counter Block RMON Transmit */ ieee_tstruct fec_ieee_t; /* 0x4248 -> 0x4277 - MIB Counter Block IEEE Transmit */ vubyte pack15[8]; /* 0x4278 -> 0x427F - RESERVED */ rmon_rstruct fec_rmon_r; /* 0x4280 -> 0x42C7 - MIB Counter Block RMON Receive */ ieee_rstruct fec_ieee_r; /* 0x42C8 -> 0x42E3 - MIB Counter Block IEEE Receive */ vubyte pack16[284]; /* 0x42E4 -> 0x43FF - RESERVED */ vudword atcr; /* 0x4400 -> 0x4403 - Timer Control Register */ vudword atvr; /* 0x4404 -> 0x4407 - Timer Value Register */ vudword atoff; /* 0x4408 -> 0x440B - Offset Value for One-Shot Event Generation */ vudword atper; /* 0x440C -> 0x440F - Timer Period */ vudword atcor; /* 0x4410 -> 0x4413 - Correction Counter Wrap-Around Value */ vudword atinc; /* 0x4414 -> 0x4417 - Timestamp Clock Period and Correction Increment */ vudword atstmp; /* 0x4418 -> 0x441B - Timestamp of Last Transmitted Frame */ vubyte pack17[228]; /* 0x441C -> 0x44FF - RESERVED */ vudword smacl0; /* 0x4500 -> 0x4503 - Supplemental MAC Address Lower 0 */ vudword smacu0; /* 0x4504 -> 0x4507 - Supplemental MAC Address Upper 0 */ vudword smacl1; /* 0x4508 -> 0x450B - Supplemental MAC Address Lower 1 */ vudword smacu1; /* 0x450C -> 0x450F - Supplemental MAC Address Upper 1 */ vudword smacl2; /* 0x4510 -> 0x4513 - Supplemental MAC Address Lower 2 */ vudword smacu2; /* 0x4514 -> 0x4517 - Supplemental MAC Address Upper 2 */ vudword smacl3; /* 0x4518 -> 0x451B - Supplemental MAC Address Lower 3 */ vudword smacu3; /* 0x451C -> 0x451F - Supplemental MAC Address Upper 3 */ vubyte pack18[15072]; /* 0x4520 -> 0x7FFF - RESERVED */ } fecstruct; /* * ETHERNET SWITCH */ typedef struct { vudword rev; /* 0xFC0D_C000 -> 0xFC0D_C003 - Revision */ vudword scr; /* 0xFC0D_C004 -> 0xFC0D_C007 - Scratch Register */ vudword per; /* 0xFC0D_C008 -> 0xFC0D_C00B - Port Enable Register */ vubyte pack00[4]; /* 0xFC0D_C00C -> 0xFC0D_C00F - RESERVED */ vudword vlanv; /* 0xFC0D_C010 -> 0xFC0D_C013 - VLAN Verify */ vudword dbcr; /* 0xFC0D_C014 -> 0xFC0D_C017 - Default Broadcast Resolution */ vudword dmcr; /* 0xFC0D_C018 -> 0xFC0D_C01B - Default Multicast Resolution */ vudword bklr; /* 0xFC0D_C01C -> 0xFC0D_C01F - Blocking and Learning Enable */ vudword bmpc; /* 0xFC0D_C020 -> 0xFC0D_C023 - Bridge Management Port Configuration */ vudword mode; /* 0xFC0D_C024 -> 0xFC0D_C027 - Mode Configuration */ vudword vimsel; /* 0xFC0D_C028 -> 0xFC0D_C02B - VLAN Input Manipulation Select */ vudword vomsel; /* 0xFC0D_C02C -> 0xFC0D_C02F - VLAN Output Manipulation Select */ vudword vimen; /* 0xFC0D_C030 -> 0xFC0D_C033 - VLAN Input Manipulation Enable */ vudword vid; /* 0xFC0D_C034 -> 0xFC0D_C037 - VLAN Tag ID */ vubyte pack01[8]; /* 0xFC0D_C038 -> 0xFC0D_C03F - RESERVED */ vudword mcr; /* 0xFC0D_C040 -> 0xFC0D_C043 - Mirror Control Register */ vudword egmap; /* 0xFC0D_C044 -> 0xFC0D_C047 - Egress Port Definitions */ vudword ingmap; /* 0xFC0D_C048 -> 0xFC0D_C04B - Ingress Port Definitions */ vudword ingsal; /* 0xFC0D_C04C -> 0xFC0D_C04F - Ingress Source MAC Address Low */ vudword ingsah; /* 0xFC0D_C050 -> 0xFC0D_C053 - Ingress Source MAC Address High */ vudword ingdal; /* 0xFC0D_C054 -> 0xFC0D_C057 - Ingress Destination MAC Address Low */ vudword ingdah; /* 0xFC0D_C058 -> 0xFC0D_C05B - Ingress Destination MAC Address High */ vudword egsal; /* 0xFC0D_C05C -> 0xFC0D_C05F - Egress Source MAC Address Low */ vudword egsah; /* 0xFC0D_C060 -> 0xFC0D_C063 - Egress Source MAC Address High */ vudword egdal; /* 0xFC0D_C064 -> 0xFC0D_C067 - Egress Destination MAC Address Low */ vudword egdah; /* 0xFC0D_C068 -> 0xFC0D_C06B - Egress Destination MAC Address High */ vudword mcval; /* 0xFC0D_C06C -> 0xFC0D_C06F - Mirror Count Value */ vubyte pack02[16]; /* 0xFC0D_C070 -> 0xFC0D_C07F - RESERVED */ vudword mmsr; /* 0xFC0D_C080 -> 0xFC0D_C083 - Memory Manager Status */ vudword lmt; /* 0xFC0D_C084 -> 0xFC0D_C087 - Low Memory Threshold */ vudword lfc; /* 0xFC0D_C088 -> 0xFC0D_C08B - Lowest Number of Free Cells */ vudword pcsr; /* 0xFC0D_C08C -> 0xFC0D_C08F - Port Congestion Status */ vudword iosr; /* 0xFC0D_C090 -> 0xFC0D_C093 - Switch Input and Output Interface Status */ vudword qwt; /* 0xFC0D_C094 -> 0xFC0D_C097 - Queue Weights */ vubyte pack03[4]; /* 0xFC0D_C098 -> 0xFC0D_C09B - RESERVED */ vudword p0bct; /* 0xFC0D_C09C -> 0xFC0D_C09F - Port 0 Backpressure Congestion Threshold */ vubyte pack04[28]; /* 0xFC0D_C0A0 -> 0xFC0D_C0BB - RESERVED */ vudword ffen; /* 0xFC0D_C0BC -> 0xFC0D_C0BF - Port 0 Forced Forwarding Enable */ vudword psnp1; /* 0xFC0D_C0C0 -> 0xFC0D_C0C3 - Port Snooping Register 1 */ vudword psnp2; /* 0xFC0D_C0C4 -> 0xFC0D_C0C7 - Port Snooping Register 2 */ vudword psnp3; /* 0xFC0D_C0C8 -> 0xFC0D_C0CB - Port Snooping Register 3 */ vudword psnp4; /* 0xFC0D_C0CC -> 0xFC0D_C0CF - Port Snooping Register 4 */ vudword psnp5; /* 0xFC0D_C0D0 -> 0xFC0D_C0D3 - Port Snooping Register 5 */ vudword psnp6; /* 0xFC0D_C0D4 -> 0xFC0D_C0D7 - Port Snooping Register 6 */ vudword psnp7; /* 0xFC0D_C0D8 -> 0xFC0D_C0DB - Port Snooping Register 7 */ vudword psnp8; /* 0xFC0D_C0DC -> 0xFC0D_C0DF - Port Snooping Register 8 */ vudword ipsnp1; /* 0xFC0D_C0E0 -> 0xFC0D_C0E3 - IP Snooping Register 1 */ vudword ipsnp2; /* 0xFC0D_C0E4 -> 0xFC0D_C0E7 - IP Snooping Register 2 */ vudword ipsnp3; /* 0xFC0D_C0E8 -> 0xFC0D_C0EB - IP Snooping Register 3 */ vudword ipsnp4; /* 0xFC0D_C0EC -> 0xFC0D_C0EF - IP Snooping Register 4 */ vudword ipsnp5; /* 0xFC0D_C0F0 -> 0xFC0D_C0F3 - IP Snooping Register 5 */ vudword ipsnp6; /* 0xFC0D_C0F4 -> 0xFC0D_C0F7 - IP Snooping Register 6 */ vudword ipsnp7; /* 0xFC0D_C0F8 -> 0xFC0D_C0FB - IP Snooping Register 7 */ vudword ipsnp8; /* 0xFC0D_C0FC -> 0xFC0D_C0FF - IP Snooping Register 8 */ vudword p0vres; /* 0xFC0D_C100 -> 0xFC0D_C103 - Port 0 VLAN Priority Resolution Map */ vudword p1vres; /* 0xFC0D_C104 -> 0xFC0D_C107 - Port 1 VLAN Priority Resolution Map */ vudword p2vres; /* 0xFC0D_C108 -> 0xFC0D_C10B - Port 2 VLAN Priority Resolution Map */ vubyte pack05[52]; /* 0xFC0D_C10C -> 0xFC0D_C13F - RESERVED */ vudword ipres; /* 0xFC0D_C140 -> 0xFC0D_C143 - IPv4/v6 Priority Resolution Table */ vubyte pack06[60]; /* 0xFC0D_C144 -> 0xFC0D_C17F - RESERVED */ vudword p0res; /* 0xFC0D_C180 -> 0xFC0D_C183 - Port 0 Priority Resolution Configuration */ vudword p1res; /* 0xFC0D_C184 -> 0xFC0D_C187 - Port 1 Priority Resolution Configuration */ vudword p2res; /* 0xFC0D_C188 -> 0xFC0D_C18B - Port 2 Priority Resolution Configuration */ vubyte pack07[116]; /* 0xFC0D_C18C -> 0xFC0D_C1FF - RESERVED */ vudword p0id; /* 0xFC0D_C200 -> 0xFC0D_C203 - Port 0 VLAN ID */ vudword p1id; /* 0xFC0D_C204 -> 0xFC0D_C207 - Port 1 VLAN ID */ vudword p2id; /* 0xFC0D_C208 -> 0xFC0D_C20B - Port 2 VLAN ID */ vubyte pack08[116]; /* 0xFC0D_C20C -> 0xFC0D_C27F - RESERVED */ vudword vres[32]; /* 0xFC0D_C280 -> 0xFC0D_C2FF - VLAN Domain Resolution Entry 0-31 */ vudword discn; /* 0xFC0D_C300 -> 0xFC0D_C303 - Number of Discarded Frames */ vudword discb; /* 0xFC0D_C304 -> 0xFC0D_C307 - Bytes of Discarded Frames */ vudword ndiscn; /* 0xFC0D_C308 -> 0xFC0D_C30B - Number of Non-Discarded Frames */ vudword ndiscb; /* 0xFC0D_C30C -> 0xFC0D_C30F - Bytes of Non-Discarded Frames */ vudword p0oqc; /* 0xFC0D_C310 -> 0xFC0D_C313 - Port 0 Output Queue Congestion */ vudword p0mvid; /* 0xFC0D_C314 -> 0xFC0D_C317 - Port 0 Mismatching VLAN ID */ vudword p0mvtag; /* 0xFC0D_C318 -> 0xFC0D_C31B - Port 0 Missing VLAN Tag */ vudword p0bl; /* 0xFC0D_C31C -> 0xFC0D_C31F - Port 0 Blocked */ vudword p1oqc; /* 0xFC0D_C320 -> 0xFC0D_C323 - Port 1 Output Queue Congestion */ vudword p1mvid; /* 0xFC0D_C324 -> 0xFC0D_C327 - Port 1 Mismatching VLAN ID */ vudword p1mvtag; /* 0xFC0D_C328 -> 0xFC0D_C32B - Port 1 Missing VLAN Tag */ vudword p1bl; /* 0xFC0D_C32C -> 0xFC0D_C32F - Port 1 Blocked */ vudword p2oqc; /* 0xFC0D_C330 -> 0xFC0D_C333 - Port 2 Output Queue Congestion */ vudword p2mvid; /* 0xFC0D_C334 -> 0xFC0D_C337 - Port 2 Mismatching VLAN ID */ vudword p2mvtag; /* 0xFC0D_C338 -> 0xFC0D_C33B - Port 2 Missing VLAN Tag */ vudword p2bl; /* 0xFC0D_C33C -> 0xFC0D_C33F - Port 2 Blocked */ vubyte pack09[192]; /* 0xFC0D_C340 -> 0xFC0D_C3FF - RESERVED */ vudword isr; /* 0xFC0D_C400 -> 0xFC0D_C403 - Interrupt Status Register */ vudword imr; /* 0xFC0D_C404 -> 0xFC0D_C407 - Interrupt Mask Register */ vudword rdsr; /* 0xFC0D_C408 -> 0xFC0D_C40B - Receive Descriptor Ring Pointer */ vudword tdsr; /* 0xFC0D_C40C -> 0xFC0D_C40F - Transmit Descriptor Ring Pointer */ vudword mrbr; /* 0xFC0D_C410 -> 0xFC0D_C413 - Maximum Receive Buffer Size */ vudword rdar; /* 0xFC0D_C414 -> 0xFC0D_C417 - Receive Descriptor Active */ vudword tdar; /* 0xFC0D_C418 -> 0xFC0D_C41B - Transmit Descriptor Active */ vubyte pack10[228]; /* 0xFC0D_C41C -> 0xFC0D_C4FF - RESERVED */ vudword lrec0; /* 0xFC0D_C500 -> 0xFC0D_C503 - Learning Records A0 & B1 */ vudword lrec1; /* 0xFC0D_C504 -> 0xFC0D_C507 - Learning Record B1 */ vudword lsr; /* 0xFC0D_C508 -> 0xFC0D_C50B - Learning Data Available Status */ vubyte pack11[15092]; /* 0xFC0D_C50C -> 0xFC0D_FFFF - RESERVED */ vudword maclook[4096]; /* 0xFC0E_0000 -> 0xFC0E_3FFF - MAC Address Lookup Table */ } eswstruct; /* * NAND FLASH CONTROLLER */ typedef struct { vudword sramb0[576]; /* 0xFC0F_C000 -> 0xFC0F_C8FF - SRAM Buffer 0 */ vubyte pack00[1792]; /* 0xFC0F_C900 -> 0xFC0F_CFFF - RESERVED */ vudword sramb1[576]; /* 0xFC0F_D000 -> 0xFC0F_D8FF - SRAM Buffer 1 */ vubyte pack01[1792]; /* 0xFC0F_D900 -> 0xFC0F_DFFF - RESERVED */ vudword sramb2[576]; /* 0xFC0F_E000 -> 0xFC0F_E8FF - SRAM Buffer 2 */ vubyte pack02[1792]; /* 0xFC0F_E900 -> 0xFC0F_EFFF - RESERVED */ vudword sramb3[576]; /* 0xFC0F_F000 -> 0xFC0F_F8FF - SRAM Buffer 3 */ vubyte pack03[1536]; /* 0xFC0F_F900 -> 0xFC0F_FEFF - RESERVED */ vudword cmd1; /* 0xFC0F_FF00 -> 0xFC0F_FF03 - Flash Command 1 */ vudword cmd2; /* 0xFC0F_FF04 -> 0xFC0F_FF07 - Flash Command 2 */ vudword car; /* 0xFC0F_FF08 -> 0xFC0F_FF0B - Column Address */ vudword rar; /* 0xFC0F_FF0C -> 0xFC0F_FF0F - Row Address */ vudword rpt; /* 0xFC0F_FF10 -> 0xFC0F_FF13 - Flash Command Repeat */ vudword rai; /* 0xFC0F_FF14 -> 0xFC0F_FF17 - Row Address Increment */ vudword sr1; /* 0xFC0F_FF18 -> 0xFC0F_FF1B - Flash Status 1 */ vudword sr2; /* 0xFC0F_FF1C -> 0xFC0F_FF1F - Flash Status 2 */ vudword dma1; /* 0xFC0F_FF20 -> 0xFC0F_FF23 - DMA 1 Address Register */ vudword dmacfg; /* 0xFC0F_FF24 -> 0xFC0F_FF27 - DMA Configuration Register */ vudword swap; /* 0xFC0F_FF28 -> 0xFC0F_FF2B - Cache Swap Register */ vudword secsz; /* 0xFC0F_FF2C -> 0xFC0F_FF2F - Sector Size Register */ vudword cfg; /* 0xFC0F_FF30 -> 0xFC0F_FF33 - Flash Configuration Register */ vudword dma2; /* 0xFC0F_FF34 -> 0xFC0F_FF37 - DMA 2 Address Register */ vudword isr; /* 0xFC0F_FF38 -> 0xFC0F_FF3B - Interrupt Status Register */ } nfcstruct; /* * MCF54418 MAIN STRUCT 1 */ typedef struct { owstruct ow; /* 0xEC00_8000 -> 0xEC00_801B - 1-Wire Module */ vubyte pack01[32740]; /* 0xEC00_801C -> 0xEC00_FFFF */ i2cstruct i2c25[4]; /* 0xEC01_0000 -> 0xEC01_FFFF - I2C Module 2-5 */ vubyte pack02[98304]; /* 0xEC02_0000 -> 0xEC03_7FFF */ dspistruct dspi2; /* 0xEC03_8000 -> 0xEC03_80BB - DMA Serial Peripheral Interface 2 */ vubyte pack03[16196]; /* 0xEC03_80BC -> 0xEC03_BFFF */ dspistruct dspi3; /* 0xEC03_C000 -> 0xEC03_C0BB - DMA Serial Peripheral Interface 3 */ vubyte pack04[147268]; /* 0xEC03_C0BC -> 0xEC05_FFFF */ uartstruct uarts[6]; /* 0xEC06_0000 -> 0xEC07_7FFF - UART Module 4-9 */ vubyte pack05[65536]; /* 0xEC07_8000 -> 0xEC08_7FFF */ mcpwmstruct mcpwm; /* 0xEC08_8000 -> 0xEC08_8153 - Motor Control Pulse-Width Modulator */ vubyte pack06[32428]; /* 0xEC08_8154 -> 0xEC08_FFFF */ resetstruct reset; /* 0xEC09_0000 -> 0xEC09_0003 - Reset Controller */ ccmstruct ccm; /* 0xEC09_0004 -> 0xEC09_0027 - Chip Configuration Module */ vubyte pack07[16344]; /* 0xEC09_0028 -> 0xEC09_3FFF */ gpiostruct gpio; /* 0xEC09_4000 -> 0xEC09_4087 - Pin-Multiplexing and Control */ } mcf54418_1; /* * MCF54418 MAIN STRUCT 2 */ typedef struct { xbsstruct xbs; /* 0xFC00_4000 -> 0xFC00_4713 - Crossbar Switch (XBS) */ vubyte pack09[14572]; /* 0xFC00_4714 -> 0xFC00_7FFF */ csstruct cs[6]; /* 0xFC00_8000 -> 0xFC00_8047 - Chip Select 0-5 */ vubyte pack10[98232]; /* 0xFC00_8048 -> 0xFC01_FFFF */ canstruct can[2]; /* 0xFC02_0000 -> 0xFC02_7FFF - Controller Area Network (FlexCAN) 0-1 */ vubyte pack11[65536]; /* 0xFC02_8000 -> 0xFC03_7FFF */ i2cstruct i2c1; /* 0xFC03_8000 -> 0xFC03_8013 - I2C Module 1 */ // vubyte pack12[16364]; /* 0xFC03_8014 -> 0xFC03_BFFF */ dspistruct dspi1; /* 0xFC03_C000 -> 0xFC03_C0BB - DMA Serial Peripheral Interface 1 */ vubyte pack13[16212]; /* 0xFC03_C0BC -> 0xFC04_000F */ scmstruct scm; /* 0xFC04_0010 -> 0xFC04_007F - System Control Module and Power Management */ vubyte pack14[16256]; /* 0xFC04_0080 -> 0xFC04_3FFF */ edmastruct edma; /* 0xFC04_4000 -> 0xFC04_57FF - Enhanced Direct Memory Access Controller */ vubyte pack15[10240]; /* 0xFC04_5800 -> 0xFC04_7FFF */ intcstruct intc[3]; /* 0xFC04_8000 -> 0xFC05_3FFF - Interrupt Controller 0-2 */ vubyte pack16[224]; /* 0xFC05_4000 -> 0xFC05_40DF */ intc_iackstruct intc_iack; /* 0xFC05_40E0 -> 0xFC05_40FF - Global Interrupt Acknowledge Cycles */ vubyte pack17[16128]; /* 0xFC05_4100 -> 0xFC05_7FFF */ i2cstruct i2c0; /* 0xFC05_8000 -> 0xFC05_8013 - I2C Module 0 */ // vubyte pack18[16364]; /* 0xFC05_8014 -> 0xFC05_BFFF */ dspistruct dspi0; /* 0xFC05_C000 -> 0xFC05_C0BB - DMA Serial Peripheral Interface 0 */ vubyte pack19[16196]; /* 0xFC05_C0BC -> 0xFC05_FFFF */ uartstruct uarts[4]; /* 0xFC06_0000 -> 0xFC06_FFFF - UART Module 0-3 */ timerstruct timer[4]; /* 0xFC07_0000 -> 0xFC07_FFFF - DMA Timer Module 0-3 */ pitstruct pit[4]; /* 0xFC08_0000 -> 0xFC08_FFFF - Programmable Interrupt Timer Module 0-3 */ eportstruct eport; /* 0xFC09_0000 -> 0xFC09_0007 - Edge Port Module */ vubyte pack20[16376]; /* 0xFC09_0008 -> 0xFC09_3FFF */ adcstruct adc; /* 0xFC09_4000 -> 0xFC09_405B - Analog-to-Digital Converter */ vubyte pack21[16292]; /* 0xFC09_405C -> 0xFC09_7FFF */ dacstruct dac[2]; /* 0xFC09_8000 -> 0xFC09_FFFF - Digital-to-Analog Converter */ vubyte pack22[32]; /* 0xFC0A_0000 -> 0xFC0A_001F */ sbfstruct sbf; /* 0xFC0A_0020 -> 0xFC0A_0023 - Serial Boot Facility */ vubyte pack23[32732]; /* 0xFC0A_0024 -> 0xFC0A_7FFF */ rtcstruct rtc; /* 0xFC0A_8000 -> 0xFC0A_883F - Real-Time Clock */ vubyte pack24[14272]; /* 0xFC0A_8840 -> 0xFC0A_BFFF */ simstruct sim; /* 0xFC0A_C000 -> 0xFC0A_C07B - Subscriber Identification Module */ vubyte pack25[16260]; /* 0xFC0A_C07C -> 0xFC0A_FFFF */ usb_otgstruct usb_otg; /* 0xFC0B_0000 -> 0xFC0B_01CF - USB On-the-Go */ vubyte pack26[15920]; /* 0xFC0B_01D0 -> 0xFC0B_3FFF */ usb_hoststruct usb_host; /* 0xFC0B_4000 -> 0xFC0B_41AB - USB Host Controller */ vubyte pack27[15956]; /* 0xFC0B_41AC -> 0xFC0B_7FFF */ ddrmcstruct ddrmc; /* 0xFC0B_8000 -> 0xFC0B_81AF - DDR1/2 SDRAM Memory Controller */ vubyte pack28[15952]; /* 0xFC0B_81B0 -> 0xFC0B_BFFF */ ssi0struct ssi0; /* 0xFC0B_C000 -> 0xFC0B_C05B - Synchronous Serial Interface 0 */ vubyte pack29[16292]; /* 0xFC0B_C05C -> 0xFC0B_FFFF */ clockstruct clock; /* 0xFC0C_0000 -> 0xFC0C_000B - Clock Module (Phase-Locked Loop) */ vubyte pack30[16372]; /* 0xFC0C_000C -> 0xFC0C_3FFF */ rngstruct rng; /* 0xFC0C_4000 -> 0xFC0C_401B - Random Number Generator */ vubyte pack31[16356]; /* 0xFC0C_401C -> 0xFC0C_7FFF */ ssi1struct ssi1; /* 0xFC0C_8000 -> 0xFC0C_805B - Synchronous Serial Interface 1 */ vubyte pack32[16292]; /* 0xFC0C_805C -> 0xFC0C_BFFF */ sdhcstruct sdhc; /* 0xFC0C_C000 -> 0xFC0C_C0FF - Enhanced Secure Digital Host Controller */ vubyte pack33[32512]; /* 0xFC0C_C100 -> 0xFC0D_3FFF */ fecstruct fec[2]; /* 0xFC0D_4000 -> 0xFC0D_BFFF - 10/100 Mbps Ethernet MAC-NET Core 0-1 */ eswstruct esw; /* 0xFC0D_C000 -> 0xFC0E_3FFF - Ethernet Switch */ vubyte pack36[98304]; /* 0xFC0E_4000 -> 0xFC0F_BFFF */ nfcstruct nfc; /* 0xFC0F_C000 -> 0xFC0F_FF3B - NAND Flash Controller */ } mcf54418_2; extern vudword flash_mirror[0x80000]; extern volatile rgpiostruct sim_rgpio; extern volatile mcf54418_1 sim1; extern volatile mcf54418_2 sim2; typedef struct { unsigned long table[255]; } vectors; extern vectors vector_base; typedef struct { unsigned short flags; unsigned short length; unsigned long address; } EtherBD; #define RXBD_Flag_Empty ( 0x8000 ) #define RXBD_Flag_SW1b ( 0x4000 ) #define RXBD_Flag_Wrap ( 0x2000 ) #define RXBD_Flag_SW2b ( 0x1000 ) #define RXBD_Flag_Last ( 0x0800 ) #define RXBD_Flag_Miss ( 0x0100 ) #define RXBD_Flag_BroadCast ( 0x0080 ) #define RXBD_Flag_MultiCast ( 0x0040 ) #define RXBD_Flag_LengthErr ( 0x0020 ) #define RXBD_Flag_Align_Err ( 0x0010 ) #define RXBD_Flag_ShortErr ( 0x0008 ) #define RXBD_Flag_CRC_Err ( 0x0004 ) #define RXBD_Flag_OverErr ( 0x0002 ) #define RXBD_Flag_TruncErr ( 0x0001 ) #define RXBD_Error_Mask ( RXBD_Flag_LengthErr | RXBD_Flag_Align_Err | \ RXBD_Flag_ShortErr | RXBD_Flag_CRC_Err | \ RXBD_Flag_OverErr | RXBD_Flag_TruncErr ) #define TXBD_Flag_Ready ( 0x8000 ) #define TXBD_Flag_SW1b ( 0x4000 ) #define TXBD_Flag_Wrap ( 0x2000 ) #define TXBD_Flag_SW2b ( 0x1000 ) #define TXBD_Flag_Last ( 0x0800 ) #define TXBD_Flag_TxCRC ( 0x0400 ) #define TXBD_Flag_Defered ( 0x0200 ) #define TXBD_Flag_HB_Error ( 0x0100 ) #define TXBD_Flag_LC_Error ( 0x0080 ) #define TXBD_Flag_RT_Error ( 0x0040 ) #define TXBD_Flag_RC_B3 ( 0x0020 ) #define TXBD_Flag_RC_B2 ( 0x0010 ) #define TXBD_Flag_RC_B1 ( 0x0008 ) #define TXBD_Flag_RC_B0 ( 0x0004 ) #define TXBD_Flag_UN_Error ( 0x0002 ) #define TXBD_Flag_CSL_Error ( 0x0001 ) #define TXBD_Error_Mask ( TXBD_Flag_UN_Error | TXBD_Flag_RT_Error | \ TXBD_Flag_LC_Error | TXBD_Flag_HB_Error ) #define TXBD_Flag_NormalSend ( TXBD_Flag_TxCRC | TXBD_Flag_Ready | \ TXBD_Flag_Last ) #define FEC_ISR_MASK_HBERR ( 0x80000000 ) #define FEC_ISR_MASK_BABR ( 0x40000000 ) #define FEC_ISR_MASK_BABT ( 0x20000000 ) #define FEC_ISR_MASK_GRA ( 0x10000000 ) #define FEC_ISR_MASK_TXF ( 0x08000000 ) #define FEC_ISR_MASK_TXB ( 0x04000000 ) #define FEC_ISR_MASK_RXF ( 0x02000000 ) #define FEC_ISR_MASK_RXB ( 0x01000000 ) #define FEC_ISR_MASK_MII ( 0x00800000 ) #define FEC_ISR_MASK_EBERR ( 0x00400000 ) #define FEC_ISR_MASK_LC ( 0x00200000 ) #define FEC_ISR_MASK_RL ( 0x00100000 ) #define FEC_ISR_MASK_UN ( 0x00080000 ) #endif /* _SIM54418_H_ */