Hello,
I'm laying out a PCB for my SB70LC to plug into. I've have looked high and low (pardon the pun) but cannot find any straightforward information on pin pull-ups/pull-downs. I am used to Freescale MCUs having built-in "pull enable" settings, but these ColdFire MCUs don't seem to support that.
If pins are unused, how should they be pulled, and by what (value)?
If I am using a pin as an input and want to pull it normally low, and then have an external source pull it high once in a while, what kind of internal impedance should I expect to overcome (again, what resistor values are commonly used with these modules)?
(Or are these pins, when set to GPIO, always at high impedance?)
Thank you.
Pin Pull-ups/Pull-downs
Re: Pin Pull-ups/Pull-downs
Hi,
The reset configuration of the GPIO multiplexed pins is input GPIO. The only pins going to the SB70LC header that are changed by the boot monitor are the RX and TX pins of the selected boot UART, this is UART0 by default.
There is a small footnote at the bottom of table 12-1 in the reference manual: "Refers to pin’s primary function. All pins which are configurable for GPIO have a pullup enabled in GPIO mode with the exception of PBUSCTL[7], PBUSCTL[4:0], PADDR, PBS, PSDRAM." I have also not gotten a consistent answer from Freescale of what the pull-up values are and as you found out they do not document this well. Through some testing I have found these pull-up values to be around 10K but you may want to confirm this. They are definitely pulled up internally so if the pin is unused you should be able to leave it unconnected. The reset input has an on-board 4.7K pull-up.
-Larry
The reset configuration of the GPIO multiplexed pins is input GPIO. The only pins going to the SB70LC header that are changed by the boot monitor are the RX and TX pins of the selected boot UART, this is UART0 by default.
There is a small footnote at the bottom of table 12-1 in the reference manual: "Refers to pin’s primary function. All pins which are configurable for GPIO have a pullup enabled in GPIO mode with the exception of PBUSCTL[7], PBUSCTL[4:0], PADDR, PBS, PSDRAM." I have also not gotten a consistent answer from Freescale of what the pull-up values are and as you found out they do not document this well. Through some testing I have found these pull-up values to be around 10K but you may want to confirm this. They are definitely pulled up internally so if the pin is unused you should be able to leave it unconnected. The reset input has an on-board 4.7K pull-up.
-Larry
Re: Pin Pull-ups/Pull-downs
Thank you for your response. I have experimented with pins 3-8 and 15-17 (set to GPIO) on my SB70LC and my calculations point to internal CPU pullups of about 40K ohms.
(July 2011 edit) Although, now that I've gotten and played with other SB70LC boards over time, I seem to find different pullup values closer to what lgitlitz mentions... Did I mis-measure/calculate before or is there a wide variance? Hmmm...
(July 2011 edit) Although, now that I've gotten and played with other SB70LC boards over time, I seem to find different pullup values closer to what lgitlitz mentions... Did I mis-measure/calculate before or is there a wide variance? Hmmm...